F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/01/2022
Public

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6.6. Avalon® Streaming Flow Control Signals

Table 23.   Avalon® Streaming Flow Control Signals
Signal Direction Width Description
avalon_st_pause_data[] In 2

This signal takes effect when the register bits, tx_pauseframe_enable[2:1], are both set to the default value 0.

Set this signal to the following values to trigger the corresponding actions.
  • 0x0: Stops pause frame generation.
  • 0x1: Generates an XON pause frame.
  • 0x2: Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3: Reserved.