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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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6.5.1. Avalon® Streaming TX Data Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
avalon_st_tx_startofpacket | In | 1 | Assert this signal to indicate the beginning of the TX data. |
avalon_st_tx_endofpacket | In | 1 | Assert this signal to indicate the end of the TX data. |
avalon_st_tx_valid | In | 1 | Assert this signal to indicate that the avalon_st_tx_data[] signal and other signals on this interface are valid. |
avalon_st_tx_ready | Out | 1 | When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic.
Note: During reset, the value of the this signal can be 0 or 1.
|
avalon_st_tx_error | In | 1 | Assert this signal to indicate that the current TX packet contains errors. |
avalon_st_tx_data[] | In | 32/64 | TX data from the client. The client sends the TX data to the MAC IP core in this order: avalon_st_tx_data[31:24], avalon_st_tx_data[23:16], and so forth. The width is 64 bits when you enable the Use 64-bit Ethernet 10G MAC Avalon® streaming interface option. Otherwise, it is 32 bits |
avalon_st_tx_empty[] | In | 2/3 | Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.
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