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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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4.4.8. TX Timing Diagrams
Figure 13. Normal FrameThe following diagram shows the transmission of a normal frame.
Figure 14. Normal Frame with Padding Bytes Insertion and Legacy Ethernet 10G MAC Avalon Streaming Interface EnabledThe following diagram shows the transmission of good frames with padding bytes insertion and legacy Ethernet 10G MAC Avalon streaming interface enabled.
Figure 15. Back-to-back Frames TransmissionThe following diagram shows back-to-back of normal frames.
Figure 16. Short Frame with TX Pad Insertion EnabledThe following diagram shows the transmission of a short frame with no payload data. Padding bytes insertion is enabled.
Figure 17. Error Condition—TX UnderflowThe following diagram shows an underflow on the transmit datapath followed by the transmission of a normal frame.
An underflow happens in the middle of a frame that results in a premature termination on the XGMII. The remaining data from the Avalon Streaming transmit interface is still received after the underflow but the data is dropped. The transmission of the next frame is not affected by the underflow.