F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/01/2022
Public

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2.2. Features

This IP core is designed to the IEEE 802.3–2008 Ethernet Standard available on the IEEE website (www.ieee.org). All Low Latency Ethernet 10G MAC Intel® FPGA IP variations include MAC only and are in full-duplex mode. These IP variations offer the following features:

  • MAC features:
    • Full-duplex MAC in one operating mode: 10M/100M/1G/2.5G/5G/10G (USXGMII).
    • Variations for selected operating mode: Only both MAC TX and MAC RX block available.
    • Programmable promiscuous (transparent) mode.
  • Interfaces:
    • Client-side—32-bit Avalon® streaming interface.
    • Management—32-bit Avalon® memory-mapped interface.
    • PHY-side—32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII) operating mode.
  • Frame structure control features:
    • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100, 88A8, 88F5, 9100, 9200).
    • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
    • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications.
    • Supports programmable IPG.
    • Ethernet flow control using pause frames.
    • Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).
    • Optional padding insertion on the TX datapath and termination on the RX datapath.
  • Frame monitoring and statistics:
    • Optional CRC checking and forwarding on the RX datapath.
    • Optional statistics collection on TX and RX datapaths.