0x0040 |
tx_pauseframe_control |
- Bits 1:0—configures the transmission of pause frames.
00: No pause frame transmission. 01: Trigger the transmission of an XON pause frame (pause quanta = 0), if the transmission is not disabled by other conditions. 10: Trigger the transmission of an XOFF pause frame (pause quanta = tx_pauseframe_quanta register), if the transmission is not disabled by other conditions. 11: Reserved. This setting does not trigger any action.
- Bits 31:2—reserved.
Changes to this self-clearing register affects the next transmission of a pause frame. |
RW |
0x0 |
0x0042 |
tx_pauseframe_quanta |
- Bits 15:0—pause quanta in unit of quanta, 1 unit = 512 bits time. The MAC IP core uses this value when it generates XOFF pause frames. An XOFF pause frame with a quanta value of 0 is equivalent to an XON frame.
- Bits 31:16—reserved.
Configure this register before you enable the MAC IP core for operations. |
RW |
0x0 |
0x0043 |
tx_pauseframe_holdoff_quanta |
- Bits 15:0—specifies the gap between two consecutive transmissions of XOFF pause frames in unit of quanta, 1 unit = 512 bits time. The gap prevents back-to-back transmissions of pause frames, which may affect the transmission of data frames.
- Bits 31:16—reserved.
Configure this register before you enable the MAC IP core for operations. |
RW |
0x1 |
0x0044 |
tx_pauseframe_enable |
- Bit 0—configures the transmission of pause frames. This bit affects pause frame requests from both register and vector settings.
0: Disables pause frame transmission. 1: Enables pause frame transmission, if TX path is enabled by tx_packet_control.
- Bits 2:1—specifies the trigger for pause frame requests.
00: Accepts pause frame requests only from vector setting, avalon_st_pause_data. 01: Accepts pause frame requests only from register setting, tx_pauseframe_control. 10 / 11: Reserved.
- Bits 31:3—reserved.
Configure this register before you enable the MAC IP core for operations. |
RW |
0x1 |