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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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6.5.3. Avalon® Streaming Data Interface Clocks
Interface Signal | Mode | Use legacy Ethernet 10G MAC Avalon® streaming interface Option | Clock Signal |
---|---|---|---|
avalon_st_tx_* | 1G | On | tx_156_25_clk |
Off | tx_312_5_clk | ||
10G | On | tx_156_25_clk | |
Off | tx_312_5_clk | ||
avalon_st_rx_* | 1G | On | rx_156_25_clk |
Off | rx_312_5_clk | ||
10G | On | rx_156_25_clk | |
Off | rx_312_5_clk |