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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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4.4.4.1. Transmit Path
The MAC TX uses the default preamble bytes as defined in the IEEE802.3 specification during frame encapsulation (i.e., "packetization") process.
Note: All other modes of operations such as CRC calculation, DIC, and throughput rate must not be affected by the mode. The hardware implication is, for instance, CRC calculation must only start on the third data phase (of avalon_st_tx_data[31:0]) onwards.