Visible to Intel only — GUID: jer1641373464399
Ixiasoft
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
Visible to Intel only — GUID: jer1641373464399
Ixiasoft
4.5.4.1. Malformed RX Packets
Malformed or invalid packets are packets that contain one or more of the error conditions, as shown in the table below.
Error Condition | Error Handling Behavior |
---|---|
Has less than 13 bytes counting from START character on lane0 for 10G or PREAMBLE for <10G). | Drop the packet internally without any side effect (e.g., update statistic count). |
does not contain 4 IDLE bytes or a Sequence Order Set prior to the START character | Dropped internally without any side effect. |
START control character is not on lane0 (for 10G) | Internally drop packet whose START character is not aligned to lane0 without any side effect. |
After 4 IDLE bytes or Sequence Order Set, does not follow the packet header sequence as below:
|
Internally drop packet which does not follow the sequence. |
During transfer, data of a given lane is not a terminate control character (i.e., EFD) when the RX Control (RXC) of the lane is asserted. | Deliberately inject CRC error (implementation specific) and forward the packet to let the downstream logic handles as frame with CRC error. |
Does not contain EFD. | Insert EOP whenever a non-ERROR control character is found during packet transfer. |