F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/01/2022
Public

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4.5.4.1. Malformed RX Packets

Malformed or invalid packets are packets that contain one or more of the error conditions, as shown in the table below.
Table 12.  Malformed/Invalid RX Packets
Error Condition Error Handling Behavior
Has less than 13 bytes counting from START character on lane0 for 10G or PREAMBLE for <10G). Drop the packet internally without any side effect (e.g., update statistic count).
does not contain 4 IDLE bytes or a Sequence Order Set prior to the START character Dropped internally without any side effect.
START control character is not on lane0 (for 10G) Internally drop packet whose START character is not aligned to lane0 without any side effect.

After 4 IDLE bytes or Sequence Order Set, does not follow the packet header sequence as below:

  • 1 START byte (at lane0) for 10G, or 1 PREAMBLE byte for 10M/100M/1G in clock 0 SFD byte (at lane3) in clock 1 when RX preamble pass-through mode is disabled.
Internally drop packet which does not follow the sequence.
During transfer, data of a given lane is not a terminate control character (i.e., EFD) when the RX Control (RXC) of the lane is asserted. Deliberately inject CRC error (implementation specific) and forward the packet to let the downstream logic handles as frame with CRC error.
Does not contain EFD. Insert EOP whenever a non-ERROR control character is found during packet transfer.