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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
The Low Latency Ethernet 10G MAC Intel® FPGA IP is a configurable component that implements the IEEE 802.3-2008 specification. To build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device, you can use the Low Latency Ethernet 10G MAC Intel® FPGA IP with an Intel FPGA PHY IP or any of the supported PHYs.
The figure below shows a system with the Low Latency Ethernet 10G MAC Intel® FPGA IP.
Figure 1. Typical Application of Low Latency (LL) Ethernet 10G (10GbE) MAC
Note: Intel FPGAs implement and support the Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multi-rate Ethernet PHY (PCS + PMA) Intel® FPGA IPs to interface in a chip-to-chip or chip-to-module channel with external NBASE-T (1G/2.5G/5G/10Gb Ethernet) PHY standard devices. However, Intel FPGAs do not comply with or support these interface specifications to directly interface with the required twisted-pair copper cables such as CAT-5/6/7.