F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 720985
Date 4/01/2022
Public

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Document Table of Contents

4.1. Architecture

The Low Latency Ethernet 10G MAC Intel® FPGA IP core is a composition of the following blocks:
  • Clock and reset—Generates all the clock sources and reset signals required for the whole MAC.
  • Configuration and status registers—Stores all the physical storage elements and access interfaces of configuration and status registers, including statistic counters/registers.
  • MAC transmitter (MAC TX)—Handles transmit path operations.
  • MAC receiver (MAC RX)—Handles receive path operations.
Figure 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC Block Diagram