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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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4.1. Architecture
The Low Latency Ethernet 10G MAC Intel® FPGA IP core is a composition of the following blocks:
- Clock and reset—Generates all the clock sources and reset signals required for the whole MAC.
- Configuration and status registers—Stores all the physical storage elements and access interfaces of configuration and status registers, including statistic counters/registers.
- MAC transmitter (MAC TX)—Handles transmit path operations.
- MAC receiver (MAC RX)—Handles receive path operations.
Figure 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC Block Diagram