Visible to Intel only — GUID: fav1643271426821
Ixiasoft
Visible to Intel only — GUID: fav1643271426821
Ixiasoft
7.4. TX Configuration and Status Registers
Word Offset | Register Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x0020 | tx_packet_control |
You can change the value of this register as necessary. If the TX path is disabled while a frame is being transmitted, the MAC IP core completes the transmission before disabling the TX path. |
RW | 0x0 |
0x0022 | tx_transfer_status | The MAC sets the following bits to indicate the status of the TX datapath.
|
RO | 0x0 |
0x0024 | tx_pad_control |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x1 |
0x0026 | tx_crc_control |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x3 |
0x002A | tx_src_addr_override |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x0 |
0x002C | tx_frame_maxlength |
Configure this register before you enable the MAC IP core for operations. |
RW | 0x5EE (1518) |
0x002D | tx_vlan_detection |
|
RW | 0x0 |
0x002E 0x081E |
tx_ipg_10g |
The Unidirectional feature does not support an average IPG of 8 bytes. If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x081E. Otherwise, the word offset is 0x002E. |
RW | 0x1 |
0x002F 0x081F |
tx_ipg_10M_100M_1G |
If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x081F. Otherwise, the word offset is 0x002F. |
RW | 0x0C |
0x003E | tx_underflow_counter0 | 36-bit error counter that collects the number of truncated TX frames when TX buffer underflow persists.
To read the counter, read the lower 32 bits followed by the upper 4 bits. The IP core clears the counter after a read. |
RO | 0x0 |
0x003F | tx_underflow_counter1 |