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1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IP Cores
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
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7.1. Register Map
Word Offset | Purpose | Variation |
---|---|---|
0x0000: 0x000F | Reserved | — |
0x0010: 0x0011 | Primary MAC Address | MAC TX, MAC RX |
0x0012: 0x001D | Reserved | — |
0x0020: 0x003F | TX Configuration and Status Registers | MAC TX |
0x0040: 0x005F | TX Flow Control Registers | MAC TX |
0x0060–0x009F | Reserved | — |
0x00A0: 0x00FF | RX Configuration and Status Registers | MAC RX |
0x0140: 0x023F | Statistics Registers | MAC TX, MAC RX |
0x0240: 0x0241 | ECC Registers | MAC TX, MAC RX |