F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 720985
Date 4/01/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide 2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers 8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Low Latency Ethernet 10G MAC Operating Modes 2.4. Device Family Support 2.5. Performance and Resource Utilization
2.5. Performance and Resource Utilization x
2.5.1. Resource Utilization 2.5.2. TX and RX Latency
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
3.6.1. Designing Considerations for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP
3.6.1. Designing Considerations for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP x
3.6.1.1. Timing Constraints
3.6.1.1. Timing Constraints x
3.6.1.1.1. Pseudo-Static CSR Fields 3.6.1.1.2. Clock Crosser 3.6.1.1.3. Dual Clock FIFO
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Agilex™ Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault)
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. TX Promiscuous (Transparent) Mode 4.4.8. TX Timing Diagrams
4.4.4. XGMII Encapsulation x
4.4.4.1. Transmit Path
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. CRC and Padding Bytes Removal 4.5.6. Frame Length Checking 4.5.7. Overflow Handling 4.5.8. RX Promiscuous (Transparent) Mode 4.5.9. RX Timing Diagrams
4.5.3. Address Checking x
4.5.3.1. Unicast Frame Filtering 4.5.3.2. Multicast Frame Filtering
4.5.4. Frame Type Checking x
4.5.4.1. Malformed RX Packets 4.5.4.2. CRC Error 4.5.4.3. Address Check Error
4.5.6. Frame Length Checking x
4.5.6.1. Frame Length 4.5.6.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Avalon® Memory-Mapped Interface Programming Signals 6.5. Avalon® Streaming Data Interfaces 6.6. Avalon® Streaming Flow Control Signals 6.7. Avalon® Streaming Status Interface 6.8. PHY-side Interfaces
6.5. Avalon® Streaming Data Interfaces x
6.5.1. Avalon® Streaming TX Data Interface Signals 6.5.2. Avalon® Streaming RX Data Interface Signals 6.5.3. Avalon® Streaming Data Interface Clocks
6.7. Avalon® Streaming Status Interface x
6.7.1. Avalon® Streaming Interface TX Status Signals 6.7.2. Avalon® Streaming Interface RX Status Signals
6.8. PHY-side Interfaces x
6.8.1. XGMII TX Signals 6.8.2. XGMII RX Signals
7. Configuration Registers x
7.1. Register Map 7.2. Register Access Definition 7.3. Primary MAC Address 7.4. TX Configuration and Status Registers 7.5. Flow Control Registers 7.6. RX Configuration and Status Registers 7.7. ECC Registers 7.8. Statistics Registers
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters

You customize the Intel® FPGA IP core by specifying the parameters on the parameter editor in the Intel® Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 15.   Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
Parameter Value Description
Speed 10M/100M/1G/2.5G/5G/10G (USXGMII) Show the supported speed mode.
Datapath options TX & RX Show the datapath of MAC instance.
  • TX & RX—instantiates both MAC TX and RX.
Enable ECC on memory blocks On, Off Turn on this option to enable error detection and correction on memory blocks.
Enable supplementary address On, Off Turn on this option to enable supplementary addresses. You must also set the EN_SUPP0/1/2/3 bits in the rx_frame_control register to 1.
Enable statistics collection On, Off Turn on this option to collect statistics on the TX and RX datapaths.
Statistics counters Memory-based, Register-based Specify the implementation of the statistics counters. When you turn on Statistics collection, the default implementation of the counters is Memory-based.
  • Memory-based—selecting this option frees up logic elements. The MAC IP core does not clear memory-based counters after they are read.
  • Register-based—selecting this option frees up the memory. The MAC IP core clears register-based statistic counters after the counters are read.

Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation. Undersized frames are frames with less than 64 bytes.

TX and RX datapath Reset/Default to Enable On, Off Turn off this option to disable TX and RX datapath during startup or CSR reset.
Use legacy Ethernet 10G MAC Avalon® memory-mapped interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® memory-mapped interface.
Use legacy Ethernet 10G MAC Avalon® streaming interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming interface.
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