Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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4.4. Symmetric Cryptographic IP Core Flow

This section describes the generic flow for the Symmetric Cryptographic Intel FPGA Hard IP.
To enable the flow, the FPGA must enter the User mode and the AES/SM4 Inline Cryptographic Accelerator is in the User Configuration state.
  • You drive all the clocks into the Symmetric Cryptographic IP core.
  • You set the bits to deassert resets to the Symmetric Cryptographic IP cores.
  • You configured the IP as described in Specifying the IP Core Parameters and Options or by updating the register bits in the configuration block of the AXI-Lite interface.
  • You start creating the packets in a format specified during the IP parameter configuration.
  • You stream in the packets.
  • You collect the packets streamed out from the AES/SM4 Inline Cryptographic Accelerator and send them to your logic.
  • You must stop sending packets to the Symmetric Cryptographic IP core if any error signal is asserted in the AXI-ST interface.
  • You must then handle the error received in the AXI-ST interface.
    Note: The error handling is out of scope of the Symmetric Cryptographic IP core.
  • You can then assert the subsystem_cold_rst_n signal and reprogram the Symmetric Cryptographic IP core registers for the desired configuration. Then, deassert the subsystem_cold_rst_n signal and start streaming packets again.