Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3.2. Data Last Indicator

This section specifies the conditions for inserting the data_last_indicator signal.

When you select the Generic XTS profile, the Symmetric Cryptographic IP core must assert the data_last_indicator signal on the 2nd last data cycle to indicate the last clock cycle that requires CTS. The last clock cycle indicates through the tlast signal that CTS is required when the valid bytes within the last clock cycle are not a multiple of 16 bytes.

The below example depicts an AXI-ST interface request sent to the Symmetric Cryptographic IP core using a generic XTS profile. The last clock cycle of the request contains 4 bytes of a valid payload. When the soft logic sends the request to the AES/SM4 Inline Cryptographic Accelerator, the soft logic asserts the data_last_indicator signal one cycle before the last clock cycle. If CTS is expected in the next clock cycle, you must assert this signal. You must send the last two data cycles back-to-back if CTS is expected.

Table 27.  Generic XTS Profile Example: Asserting tlast Signal
Important: You must assert tlast when you expect the CTS in the next clock cycle.
Profile Generic XTS Generic XTS Generic XTS Generic XTS
tvalid 1 1 1 0
tlast 0 0 1 0
tkeep All 1s All 1s

0000_0000

0000_0000

0000_0000

0000_0000

0000_0000

0000_0000

0000_0000

0000_0000

0000_1111

All 0s
DATA
tdata[127:0] Data 1 Data 5 {0, Data 9[32:0]} IDLE
tdata[255:128] Data 2 Data 6 IDLE IDLE
tdata[391:256] Data 3 Data 7 IDLE IDLE
tdata[511:392] Data 4 Data 8 IDLE IDLE