Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2. AXI-ST Ready Latency

The Symmetric Cryptographic IP core implements the AXI-ST ready latency on the AXI-ST TX ingress responder. The supported range of ready latency is 0 to 15.
Figure 11. AXI-ST Ready Latency Signals
Note: The AXI-ST RX egress port always operates with a ready latency of 0 and complies with the AXI specification.