Visible to Intel only — GUID: lal1644955286660
Ixiasoft
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
Visible to Intel only — GUID: lal1644955286660
Ixiasoft
4.10. Byte Ordering
The Symmetric Cryptographic IP core implements little-endian byte order and for the packet fields such as AAD and data, where bits aes_ip_app_tx_tdata[7:0] contains the first byte of the corresponding field.
Ethernet Packet Field | Cryptographic Field | Cryptographic Interface p0_app_ip_tx_tdata |
---|---|---|
N/A | IV[7:0] | [7:0] |
N/A | IV[15:8] | [15:8] |
N/A | IV[23:16] | [23:16] |
N/A | IV[31:24] | [31:24] |
N/A | IV[39:32] | [39:32] |
N/A | IV[47:40] | [47:40] |
N/A | IV[55:48] | [55:48] |
N/A | IV[63:56] | [63:56] |
N/A | IV[71:64] | [71:64] |
N/A | IV[79:72] | [79:72] |
N/A | IV[87:80] | [87:80] |
N/A | IV[95:88] | [95:88] |
N/A | AAD_LEN[7:0] | [103:96] |
N/A | AAD_LEN[15:8] | [111:104] |
N/A | AAD_LEN[23:16] | [119:112] |
N/A | AAD_LEN[31:24] | [127:120] |
Dest_addr[47:40] | AAD[7:0] | [135:128] |
Dest_addr[39:32] | AAD[15:8] | [143:136] |
Dest_addr[31:24] | AAD[23:16] | [151:144] |
Dest_addr[23:16] | AAD[31:24] | [159:152] |
Dest_addr[15:8] | AAD[39:32] | [167:160] |
Dest_addr[7:0] | AAD[47:40] | [175:168] |
Src_addr[47:40] | AAD[55:48] | [183:176] |
Src_addr[39:32] | AAD[63:56] | [191:184] |
Src_addr[31:24] | AAD[71:64] | [199:192] |
Src_addr[23:16] | AAD[79:72] | [207:200] |
Src_addr[15:8] | AAD[87:80] | [215:208] |
Src_addr[7:0] | AAD[95:88] | [223:216] |
MACsec Ethertype[15:8] | AAD[103:96] | [231:224] |
MACsec Ethertype[7:0] | AAD[111:104] | [239:232] |
... | AAD[…:112] | […:240] |