Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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Document Table of Contents

10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.10.31 22.3 1.2.0
  • Added descriptions of new terminologies.
  • Added description for Example of a Network Storage and Confidential Computing Application figure.
  • Added description for Example of a Hybrid Security Application figure.
  • Added Theoretical Throughput as a Function of pp_ip_st_clk Clock Frequency table.
  • Revised the Design Example chapter.
2022.06.20 22.2 1.1.1
  • Added that error_clear cycle should be an standalone transaction with the intended profile, stream, or channel and is not to be mixed with a key or a data cycle.
  • Updated the IP Parameter Editor figure in Parameters.
  • Removed support for EDA ModelSim simulator.
  • Updated cryptographic code errors in Error Handling.
  • Defeatured interleaving the MACsec and XTS profile.
2022.04.13 22.1 1.1.0 Initial release.