Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern

This section describes the IPsec-specific input and output signals. The Symmetric Cryptographic IP core samples all TUSER signals at the start of the packet.
Table 37.  IP Security Pattern Interface Signals
Signal Name Direction Description
algorithm_type Input/Output Indicates the cryptographic operation mode for the corresponding cycle.
  • 0: AES
  • 1: SM4
encrypt_decrypt Input/Output Indicates the type of cryptographic operation for the corresponding cycle.
  • 0: Encrypt
  • 1: Decrypt
key_128b_256b Input/Output Indicates the key size. The signal is only valid when the key_en signal is set to 1.
  • 0: 128 bit key
  • 1: 256 bit key
Note: The SM4 algorithm only supports 128 bit key size.
pattern[2:0] Input/Output
Pattern ID: Indicates the pattern profile selected for the current clock cycle.
  • 3'b011 = IPSEC: IP Security pattern
When the signal switches from the IDLE state to the IPSEC state, indicates that the data associated in the given clock cycle is related to the IP Security. In this mode, the Symmetric Cryptographic IP core expects you to stream in the full packet until the tlast signal is asserted.

When in this mode, the profile switching on a clock by clock basis is not supported.
TID[9:0] Input/Output Indicates the channel you want to use for IPsec. This bus can also track the output packets.
TID[25:16] Input Channel ID. Indicates to the logic which Crypto channel or slot is the old packet when there are 2 packets in same cycle.
Note: If you send back-to-back packets, you must use different channels to ensure the pipeline is not affected by the new key that is being programmed.
key_en Input For IPSec profile, when key_en is set, the data field starts with the key that required for this encryption (with or without authenticate) or decryption (with or without authenticate) stream. The key_en signal must be set when the pattern switches to IPSec for one clock before data_en is asserted. In IPSec pattern, the key sizes allowed are either 128 bits or 256 bits and you must assert the wire key_128b_256b to indicate the key size. The key is always 128 bit aligned.
Where the key starts in the packet is dependent on whether the previous packet into the subsystem had trailing bytes within this clock cycle. This information is available to the logic via the TLAST, TKEEP and data_en signals.
  • When there are no trailing bytes and when the key_128b_256b indicates 128 bits, the key is present in bits [127:0] in data[511:0] and you must pad 0 to [255:128]. When key_128b_256b indicates 256 bits, the key is present in bits [255:0] of data [511:0].
  • When there are trailing bytes, the key starts from the next 128 bit aligned address.

If the key starts at bit 0, then highest 128 bits (bits 511:384) when key_en is asserted either have the AAD or the data or both for this particular IPSec packet.

Followed by the key in IPSec is a 128 bit aligned IV [96 bits] and AAD Length 32 bits indicating the size of the AAD data.

Note: The AAD and text are packed together with the AAD being byte aligned.
next_packet_en Output When the profile is IPsec and tlast is asserted with a tkeep indicating that there is at least 1 word (128 bits) of free data lines excluding the MAC, this signal indicates that a new packet starts within the same clock. The new packet is 128 bits aligned.
data_en Input Always asserted for input mode.

In output mode, indicates the corresponding clock cycle either only has data or the data following by the authentication tag (MAC).

MAC_IV_tweak_en Input Not used in the IPsec profile.
data_en,

MAC_IV_tweak_en

Output When pattern[2:0] is set to the IP Security profile, indicates that the corresponding clock cycle includes either data only, or data followed by the MAC for the corresponding channel, per TID[9:0] setting.
tlast Input/Output When set, indicates that the data ends (EOP) in the current clock cycle.
Note: The tkeep signal specifies the number of valid bytes in this cycle.
tkeep Input/Output Specifies the number of valid bytes in the current clock cycle.
Table 38.  Decoding data_en and MAC_IV_tweak_en Signals

This table describes the data field decoded based on these signals shown above.

data_en MAC_IV_tweak_en data[511:0]
data_en and MAC_IV_tweak_en as Output Signals
0 0 Reserved
0 1 Bits [127:0] contain the MAC of the requested GCM operation.

If the next_packet_en signal is 0, a new packet does not start in this clock cycle.

1 0 Bits [511:0] contain input data sent to the AES/SM4 Inline Cryptographic Accelerator. The data is any of the following: AAD sent back to your logic, cleartext or ciphertext based on the requested operation.
1 1 Bits [511:0] contain the input data sent to the AES/SM4 Inline Cryptographic Accelerator followed by 128 bits of the MAC. The data is any of the following: AAD sent back to your logic, cleartext or ciphertext based on the requested operation.

You must assert the tlast signal to indicate the end of one packet. The tkeep signal indicates the length of the valid data.

Figure 19. IPsec Profile: Input SignalsThe figure depicts a simple waveform for the IPsec input data.
Figure 20. IPsec Profile: Output SignalsThe figure depicts a simple waveform for the IPsec output data.
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