Symmetric Cryptographic Intel FPGA Hard IP User Guide

Download PDF
ID 714305
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

5.3.1. MAC Packing

After the AES/SM4 Inline Cryptographic Accelerator (ICA) performs an encryption/decryption on the incoming requests, the ICA generates 16 bytes authentication tag (MAC) and appends it to the end of the request. The generated MAC is always aligned at 16 bytes segments.

The table below depicts four possible MACsec output patterns showing the MAC location within the data bus.

Table 24.  MAC Packing
Profile MACsec   MACsec   MACsec   MACsec
MAC_IV_tweak_en 1   1   1   1
data_en 0   1   1   1
next_packet_en 1   1   1   0
tlast 1   1   1   1
num_empty_bytes 64   48 to 63   32 to 47   16 to 31
TID[9:0] Channel number   Channel number   Channel number   Channel number
DATA
data[127:0] MAC   AAD/Text   AAD/Text   AAD/Text
data[255:128] AAD/Text   MAC   AAD/Text/IDLE   AAD/Text/IDLE
data[391:256] AAD/Text   AAD/Text   MAC   AAD/Text/IDLE
data[511:393] AAD/Text   AAD/Text   AAD/Text   MAC
When the packet leaves the ICA, it may contain empty bytes between the last byte of the AAD/text and the MAC tag. The soft logic block removes any empty bytes such that the 16 bytes of MAC follows immediately after the last byte of AAD/text.
Figure 12. Output Packet Format

The table displays the MAC packing as it leaves the Symmetric Cryptographic IP core. The p_vld_data is a partial valid data and does not fully consume the entire 16 bytes. It contains some empty bytes within the 16 byte segment.

Since MAC must be 16 bytes aligned, it is followed by 5 bytes of partial data (p_vld_data) and 11 bytes of empty data is removed.

When the traffics using different profiles interleave, the output pattern for the profiles do not interleave between channels during the last cycle of the packet. For example, a 16 byte MAC always follows the last byte of a payload for the specific channel before interleaving with a request from a different channel. This behavior applies to all profiles except the MACsec profile.

Table 25.  Interleave Example: Traffic Pattern Format for MACsec and GCM ProfilesThe table shows the interleaving of MACsec and GCM profiles. In MACsec profile, the pattern format specified above is not guaranteed.
Profile MACsec GCM GCM GCM GCM MACsec
TID[15:0]

(Stream)

 0 N/A N/A N/A N/A 0
TID[9:0]

(Channel)

 1 67 67 68 68 1
DATA
Data[127:0] DATA (Pkt 0) AAD MAC AAD MAC MAC
Data[255:128] DATA (Pkt 0) DATA IDLE DATA IDLE DATA
Data[383:256] DATA (Pkt 0) DATA IDLE DATA IDLE DATA
Data[511:384] p_vld_data p_vld_data IDLE p_vld_data IDLE DATA
Table 26.  MACsec Profile Example for Egress Packet: 16 bytes MAC spread across 2 clock cyclesThe example shows the 4th segment on the first clock cycle and the 1st segment on the second clock cycle. The mac_iv_tweak_en signal asserts for both clock cycles.
Profile MACsec MACsec MACsec
TID[15:0]

(Stream)

 0 N/A N/A
TID[9:0]

(Channel)

 1 1 1
mac_iv_tweak_en 1 1 0
DATA
Data[127:0] DATA (Pkt 0) MAC, IDLE DATA (Pkt 0)
Data[255:128] DATA (Pkt 0) IDLE DATA (Pkt 0)
Data[383:256] DATA (Pkt 0) IDLE DATA (Pkt 0)
Data[511:384] p_vld_data, MAC IDLE DATA (Pkt 0)
Level Two Title