Visible to Intel only — GUID: zql1647562223140
Ixiasoft
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
Visible to Intel only — GUID: zql1647562223140
Ixiasoft
7.15. Cryptographic Internal Error Log Register
Offset | 0x4C |
Addressing Mode | 32-bits |
Description | Cryptographic error log register. |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31 | RO | 0x0 | Pack Macsec: UNC ECC -- Macsec Pack RAM Unc ECC consumed by Bridge. Bridge is unreliable. User should reset the bridge. | |
30 | RO | 0x0 | Pack Macsec: Macsec SM is in ERROR state. Requires error_clear to recover. May get here due to: - Corrupted 'state' info in RAM - unexpected total_num_bytes value (should be unreachable). - Missing SOP (Got data/eop without SOP) - Missing EOP (Got SOP without EOP) NOTE: While in ERROR state, Macsec forwards data cycles to AXI-ST as-is. | |
29 | RO | 0x0 | Pack Macsec: Protocol Err -- Got SOP/EOP error that was not flagged by Depacketizer. Or Got runt that requires 2 EOPs, or 2 SOPs to be forwarded on AXIST. | |
28 | RO | 0x0 | Depack Macsec: Unc ECC -- Macsec Unpack RAM had Unc ECC that was consumed by Bridge. Bridge is unreliable. User should reset the bridge. | |
27 | RO | 0x0 | Depack Macsec: Macsec SM is in ERROR state. Requires error_clear to recover. May get here due to: - Corrupted 'state' info in RAM - Missing SOP (Got data/eop without SOP) - Missing EOP (Got SOP without EOP) NOTE: While in ERROR state, Macsec forwards data cycles to Crypto ICA HIP as-is. | |
26:20 | Reserved | |||
19 | RO | 0x0 | Depack XTS: CTS Missing indicator: Data needs CTS, but next-to-last indicator was not set. | |
18 | RO | 0x0 | Depack XTS: CTS Back-2-back Error: next to last and last cycle are not in back2back clock cycles | |
17 | RO | 0x0 | Depack XTS: Invalid data cycle (key_en, data_en, tweak_en low) | |
16:15 | Reserved | |||
14 | RO | 0x0 | 256b egress gasket FIFO 1 overflow | |
13 | RO | 0x0 | 256b egress gasket FIFO 0 overflow | |
12 | RO | 0x0 | Pack RAM Prefetch UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 31 instead. | |
11 | RO | 0x0 | Depack RAM Prefetch UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 28 instead. | |
10 | RO | 0x0 | 256/512 Gasket | |
9 | RO | 0x0 | Stream RAM UNC ECC | |
8 | RO | 0x0 | Key RAM UNC ECC | |
7 | RO | 0x0 | Pack RAM UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 31 instead. | |
6 | RO | 0x0 | Depack RAM UNC ECC NOTE: Recommend to disable this from INT Err PIN & First ERR Log, and use Bit 28 instead. | |
5 | RO | 0x0 | MAC FIFO UNC ECC | |
4 | RO | 0x0 | MAC FIFO OVF | |
3 | RO | 0x0 | AXI ST Egress MST1 FIFO OVF | |
2 | RO | 0x0 | AXI ST Egress MST0 FIFO OVF | |
1 | RO | 0x0 | AXI ST Ingress SLV1 FIFO OVF | |
0 | RO | 0x0 | AXI ST Ingress SLV0 FIFO OVF |