Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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4.6.1. Detected Error Handling

When an error occurs, the IP core updates the tuser.error_status bit and the associated tuser.error_code bits. The IP supports two types of errors, recoverable and internal errors.

Recoverable Errors

Follow these steps to recover from a recoverable error:
  • Read the error log on the AXI-Lite interface by reading the ferr_log, pacer_log1, and pacer_log2 registers.
  • Clear the error log by writing clear on the above registers.
  • Understand and correct the cause of the error.
  • Assert the tuser.error_clear signal using the profile ID where the error occurred. This step clears the specified profile of the errors.

Internal Errors

Follow these steps to recover from an internal error:
  • Read the error log on the AXI-Lite interface by reading the ferr_log and interr_log registers.
  • Understand and correct the cause of the error.
  • Assert the subsystem_cold_rst_n reset. The signal assertion resets both, the Symmetric Cryptographic IP core and AES/SM4 Inline Cryptographic Accelerator since these errors are not recoverable.