Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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Document Table of Contents

8.1. Functional Description

The Symmetric Cryptographic Intel FPGA Hard IP design example is designed to demonstrate the capabilities of the Symmetric Cryptographic Intel FPGA Hard IP. This design example is comprised of the Crypto HIP Inline Crypto Accelerator subsystem IP as well as a specialized Validation Soft IP component (VSIP) to configure and test the Symmetric Cryptographic Intel FPGA Hard IP.

When the example design is generated, a Symmetric Cryptographic Intel FPGA Hard IP component with the default configuration settings is generated for inclusion in the example design. The VSIP component is integrated with the Symmetric Cryptographic Intel FPGA Hard IP in the top-level design called crypto_qhip_vsip_top. This is the top-level design unit for Quartus synthesis, which is used for the hardware test features of the example design.

While the same top-level design unit is used for simulation, it is not the top-level design for simulation. For simulation, the top-level design is the testbench called crypto_tb_top. The top-level testbench instantiates the top-level Quartus design. The testbench provides the clock and resets inputs that are routed to device pins in the top-level Quartus design.

The VSIP component enables multiple test configurations for the Symmetric Cryptographic Intel FPGA Hard IP. The test configurations are controlled and enabled by a set of control and status registers in the VSIP component. These registers are accessed by cross-module references in the testbench for simulation and by JTAG register reads and writes in hardware.

The following figure shows the various blocks which constitute the Crypto VSIP.

Figure 25. VSIP Block Diagram