Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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Document Table of Contents

6.1.1. MACsec Flow

A stream defines a MACsec physical port on the FPGA. The MACsec protocol is implemented for each stream with a certain number of channels allocated to each port. The MACsec data streams in 128-bit segments from each port associated with that channel.
The MACsec data flow complies with the following requirements:
  1. The 1024 channels in the AES/SM4 Inline Cryptographic Accelerator are assigned to the physical ports/streams uniquely.
  2. The Symmetric Cryptographic IP core AXI-ST port streams the data packets.
  3. For specific stream, once a packet with a given channel starts processing, the packet processing must end before a packet from a different channel can start. Each clock cycle contains data from only a single stream.
  4. Several IDLE segments between the packet end and a packet start may occur.
  5. For packets with size of 64 bytes or smaller, IDLE aligned 128-bit segments may occur until the next packet starts.
  6. Each given clock cycle supports segments of up to two packets.
Figure 14. MACsec Profile Port UsageThe figure displays the data streaming flow from ports to the FPGA. Each box represents a 128 bit segment:
  • Orange color: Indicates a DATA segment.
  • White color: Indicates an IDLE segment.
  • Yellow color: Indicates a start of packet (SOP). The number indicates the channel ID for the specific packet.