Visible to Intel only — GUID: oas1644858472437
Ixiasoft
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
Visible to Intel only — GUID: oas1644858472437
Ixiasoft
6.1.1. MACsec Flow
A stream defines a MACsec physical port on the FPGA. The MACsec protocol is implemented for each stream with a certain number of channels allocated to each port. The MACsec data streams in 128-bit segments from each port associated with that channel.
The MACsec data flow complies with the following requirements:
- The 1024 channels in the AES/SM4 Inline Cryptographic Accelerator are assigned to the physical ports/streams uniquely.
- The Symmetric Cryptographic IP core AXI-ST port streams the data packets.
- For specific stream, once a packet with a given channel starts processing, the packet processing must end before a packet from a different channel can start. Each clock cycle contains data from only a single stream.
- Several IDLE segments between the packet end and a packet start may occur.
- For packets with size of 64 bytes or smaller, IDLE aligned 128-bit segments may occur until the next packet starts.
- Each given clock cycle supports segments of up to two packets.
Figure 14. MACsec Profile Port UsageThe figure displays the data streaming flow from ports to the FPGA. Each box represents a 128 bit segment:
- Orange color: Indicates a DATA segment.
- White color: Indicates an IDLE segment.
- Yellow color: Indicates a start of packet (SOP). The number indicates the channel ID for the specific packet.