Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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4.5. Dynamically Disabling SM4 Capability

In addition to the Intel® Quartus® Prime GUI option, you may follow these steps to dynamically disable the Symmetric Cryptographic IP core's SM4 capability through the control register access:
  1. Set the sm4_disable signal.
    0x00[2] = 1'b1
  2. Set the cif_latency_pipe bits to 0x34.
    0x08[23:16] = 0x34
Follow these steps to dynamically re-enable the Symmetric Cryptographic IP core's SM4 capability:
  1. Clear the sm4_disable signal.
    0x00[2] = 1'b0
  2. Set the cif_latency_pipe bits to 0x3C.
    0x08[23:16] = 0x3C