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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
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Ixiasoft
4.5. Dynamically Disabling SM4 Capability
In addition to the Intel® Quartus® Prime GUI option, you may follow these steps to dynamically disable the Symmetric Cryptographic IP core's SM4 capability through the control register access:
- Set the sm4_disable signal.
0x00[2] = 1'b1
- Set the cif_latency_pipe bits to 0x34.
0x08[23:16] = 0x34
Follow these steps to dynamically re-enable the Symmetric Cryptographic IP core's SM4 capability:
- Clear the sm4_disable signal.
0x00[2] = 1'b0
- Set the cif_latency_pipe bits to 0x3C.
0x08[23:16] = 0x3C