Visible to Intel only — GUID: erp1663007327942
Ixiasoft
Visible to Intel only — GUID: erp1663007327942
Ixiasoft
8.8.1. Supported Boards
The example design runs in an Agilex FPGA equipped with the In-Line Crypto Accelerator (ICA) Hard IP. The Hard IP is contained within the Symmetric Cryptographic Intel FPGA Hard IP.
The Agilex FPGA must be mounted on a printed circuit board that supplies power, clocks, resets, interface connectors, switches, indicators, and other ancillary components.
In the Symmetric Cryptographic Intel FPGA Hard IP GUI, you see a drop-down menu labeled as Targeted Board for Example Design. The option "User-Designed Board" is available.
Select the "User-Designed Board" option.
Only two device pins are defined explicitly in the example design, i_board_clk and i_board_rstn .
The clock pin is to be driven with a 100 MHz clock sourced on the board. The reset pin is a user pin that can be driven by any input you choose.
The portion of the .qsf file that controls is shown below:
set_location_assignment PIN_FV52 -to i_board_rstn
set_location_assignment PIN_FK46 -to i_board_clk
When the User-Designed Board option is selected, placeholders for these assignments are inserted in the .qsf file. You should fill them in as required to match your board design.