Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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4.12. AXI-ST Multiple Packet Mode

The AXI-ST Multiple Packet Mode is supported for MACsec and IPsec profiles. The AXI specification defines the Multiple Packet Mode as following:
  • No two start of packet (SOP) within the same clock cycle.
  • No two end of packet (EOP) within the same clock cycle.
  • Two packets packed within the same clock cycle are allowed as long as both packets are from the same stream.
Table 23.  AXI-ST Multiple Packet Mode
TID 0 0 0 0
tuser port 0 port 0 port 0 port 0
tlast 0 1 1 1
tuser_last_segment0 0 1 0 1
tuser_last_segment1 0 0 1 0
tuser_last_segment2 0 0 0 0
tuser_last_segment3 0 0 0 0
tkeep

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

11111111_11111111

00000000_11111111

11111111_11111111

00000000_00000000

00000000_00000000

00000000_00000000

11111111_11111111
DATA
tdata[511:448] Data 0 Data 1 Data 2
tdata[447:384] Data 0 Data 1 Data 2
tdata[383:320] Data 0 Data 1 Data 2
tdata[319:256] Data 0 Data 1 Data 2
tdata[255:192] Data 0 Data 1 64'b0
tdata[191:128] Data 0 Data 1 Data 1
tdata[127:64] Data 0 Data 0 Data 1 Data 2
tdata[63:0] Data 0 Data 0 Data 1 Data 2