Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern

This section describes the MACsec-specific input and output signals.
Table 34.  MACsec Profile Pattern Interface Signals
Signal Name Direction Description
algorithm_type Input/Output Indicates the cryptographic operation mode for the corresponding cycle.
  • 0: AES
  • 1: SM4
encrypt_decrypt Input/Output Indicates the type of cryptographic operation for the corresponding cycle.
  • 0: Encrypt
  • 1: Decrypt
key_128b_256b Input/Output Indicates the key size. The signal is only valid when the key_en signal is set to 1.
  • 0: 128 bit key
  • 1: 256 bit key
Note: The SM4 algorithm only supports 128 bit key size.
pattern[2:0] Input/Output
Pattern ID: Indicates the pattern profile selected for the current clock cycle.
  • 3'b010 = MACSEC: MAC Security profile
When the signal switches from the IDLE state to the MACSEC state, indicates that the data associated in the given clock cycle is related to the MAC Security.
TID[9:0] Input/Output Channel ID. Available when the pattern is set to MACsec profile.

When pattern ID is set to MACsec, the channel ID indicates to the logic which cryptographic channel or slot is the packet starting at this clock is associated with.

TID[15:10] Input/Output Port/Stream ID.

Indicates the stream/port that a group or channels can be associated with. The expectation is that you associate multiple channels to a given port of up to 64 ports. On the output side, the Symmetric Cryptographic IP core does not merge or pack data belonging to channels that don’t belong to the same port together.

TID[25:16] Input/Output Channel ID when the pattern[2:0] is set to MAC Security profile.

When pattern ID is set to MACsec, the channel ID indicates to the logic which cryptographic channel or slot is the packet ending at this clock is associated with.

TID[31:26] Input/Output Port/Stream ID when the pattern[2:0] is set to MAC Security profile.

Indicates the stream/port of an ending packet when there are 2 packets in the same cycle. The expectation is that you associate multiple channels to a given port of up to 64 ports. On the output side, the Symmetric Cryptographic IP core does not merge or pack data belonging to channels that don’t belong to the same port together.

key_en Input When set and pattern[2:0] is set to the MAC Security profile, indicates that the data field contains keys to program in the key slots identified by TID[9:0]. You must set the key_128b_256b signal to specify the key size, 128 or 256 bit key.
  • If key_128b_256b = 0:

    data[511:0] = {384'dX, key[127:0]}

  • If key_128b_256b = 1:

    data[511:0] = {128'dX, key[255:0]}

where X represents don't care.

This key_en is a standalone operation per clock. You can select to send the keys at one time or individually.

Asserting this signal while data is in process is not allowed.
next_packet_en Output When the profile is MACsec and tlast is asserted with a tkeep indicating that there is at least 1 word (128 bits) of free data lines excluding the MAC, this signal indicates that a new packet starts within the same clock. The new packet is 128 bits aligned.
data_en, MAC_IV_tweak_en Input When pattern[2:0] is set to the MAC Security profile, indicates that the corresponding clock cycle includes either data only, or data with IV for the corresponding channel, per TID[9:0] setting.
data_en, MAC_IV_tweak_en Output When pattern[2:0] is set to the MAC Security profile, indicates that the corresponding clock cycle includes either data only, or data followed by the MAC for the corresponding channel, per TID[9:0] setting.
tlast Input/Output When set, indicates that the data ends (EOP) in the current clock cycle.
Note: The tkeep signal specifies the number of valid bytes in this cycle.
Table 35.  Decoding data_en and MAC_IV_tweak_en Signals

This table shows the data field decoded based on the signals described above.

data_en MAC_IV_tweak_en data[511:0]
data_en and MAC_IV_tweak_en as Input Signals
0 0 Reserved
0 1 The hardware expects you to start a new packet in this clock cycle, starting with an IV without any trailing data from the previous packet.
1 0 Bits [511:0] contain input data sent to the AES/SM4 Inline Cryptographic Accelerator. The hardware assumes that the IV was sent in a previous clock cycle.
1 1 The hardware expects the end one packet in the current clock cycle and a start of another packet. You must assert the tlast signal to indicate the end of one packet and set the tkeep signal accordingly.

The tkeep signal with tlast signal indicate the number of trailing bits before you indicate the new IV.

In the current clock cycle, bits [127:0] contain:
  • IV[95:0]
  • AAD[127:96]
data_en and MAC_IV_tweak_en as Output Signals
0 0 Reserved
0 1 Bits [127:0] contain the MAC of the requested GCM operation.
1 0 Bits [511:0] contain input data sent to the AES/SM4 Inline Cryptographic Accelerator. The data is any of the following: AAD sent back to your logic, cleartext or ciphertext based on the requested operation.
1 1 Bits [511:0] contain the input data sent to the AES/SM4 Inline Cryptographic Accelerator followed by 128 bits of the MAC. The data is any of the following: AAD sent back to your logic, cleartext or ciphertext based on the requested operation.

You must assert the tlast signal to indicate the end of one packet. The tkeep signal indicates the length of the valid data.

Figure 15. MACSec Profile: Input SignalsThe figure depicts a simple waveform for the MACsec input data.
Figure 16. MACSec Profile: Output SignalsThe figure depicts a simple waveform for the MACsec output data.
The following figures displays the data processing of a 64 byte packet.
Figure 17. MACsec Profile: 64 Byte Packet Signals
Figure 18. MACsec Profile: 64 Byte Packet Input and Output Signals
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