Symmetric Cryptographic Intel FPGA Hard IP User Guide

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ID 714305
Date 10/31/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Cryptographic IP Data Profiles 7. Configuration Registers 8. Design Example 9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives 10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
1. Introduction x
1.1. Terminology 1.2. IP Core Overview 1.3. Release Information 1.4. Device Family Support 1.5. Resource Utilization
1.2. IP Core Overview x
1.2.1. IP Core Applications
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. AXI-ST Interface 2.4. AXI-Lite Interface
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Symmetric Cryptographic IP Core Flow 4.5. Dynamically Disabling SM4 Capability 4.6. Error Handling 4.7. Error Reporting 4.8. Resetting the IP Core 4.9. Channel Definition and Allocation 4.10. Byte Ordering 4.11. AXI-ST Single Packet Mode 4.12. AXI-ST Multiple Packet Mode
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.6. Error Handling x
4.6.1. Detected Error Handling 4.6.2. Key RAM ECC Error Handling
5. Block Description x
5.1. Reset Sequencer 5.2. AXI-ST Ready Latency 5.3. AXI Adapter 5.4. Integrity Check Value Comparison
5.3. AXI Adapter x
5.3.1. MAC Packing 5.3.2. Data Last Indicator 5.3.3. Stream and Channel ID Buffering 5.3.4. TKEEP and LAST_SEGMENT Signals Generation 5.3.5. MAC Dropping on Decryption
6. Cryptographic IP Data Profiles x
6.1. MAC Security Profile (MACsec) 6.2. IP Security Profile (IPsec) 6.3. Generic GCM Profile (GCM) 6.4. Generic XTS Profile (XTS)
6.1. MAC Security Profile (MACsec) x
6.1.1. MACsec Flow 6.1.2. AXI-ST Interface Using MAC Security (MACsec) Profile Pattern
6.2. IP Security Profile (IPsec) x
6.2.1. AXI-ST Interface Using IP Security (IPsec) Profile Pattern
6.3. Generic GCM Profile (GCM) x
6.3.1. AXI- ST Interface Using Generic GCM Profile Pattern
6.4. Generic XTS Profile (XTS) x
6.4.1. AXI-ST Interface Using Generic XTS Profile Pattern
7. Configuration Registers x
7.1. Cryptographic Primary Control Register 7.2. Cryptographic Secondary Control Register 7.3. Cryptographic Primary Status Register 7.4. Cryptographic Error Status Register 7.5. Cryptographic Error Control Register 7.6. Cryptographic Packet Error Control 1 Register 7.7. Cryptographic Packet Error Control 2 Register 7.8. Cryptographic Error Code Control 1 Register 7.9. Cryptographic Error Code Control 2 Register 7.10. Cryptographic Error Code Internal Control Register 7.11. Cryptographic Internal Error Control Register 7.12. Cryptographic First Error Log Register 7.13. Cryptographic Packet Error Log 1 Register 7.14. Cryptographic Packet Error Log 2 Register 7.15. Cryptographic Internal Error Log Register 7.16. Cryptographic Wall Clock LSB Register 7.17. Cryptographic Wall Clock MSB Register 7.18. Ternary Control Register
8. Design Example x
8.1. Functional Description 8.2. Crypto VSIP Top Block Descriptions 8.3. Test Configurations 8.4. Software Requirements 8.5. Simulation Requirements 8.6. Steps to Generate the Design Example 8.7. Running Simulation Tests 8.8. Running Hardware Tests
8.2. Crypto VSIP Top Block Descriptions x
8.2.1. Clock and Reset 8.2.2. Host Interface
8.7. Running Simulation Tests x
8.7.1. Steps to Simulate the Design Example
8.8. Running Hardware Tests x
8.8.1. Supported Boards 8.8.2. Steps to Compile the Design Example for Hardware 8.8.3. Steps to Run the Design Example on Hardware
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide

5.3.3. Stream and Channel ID Buffering

The AES/SM4 Inline Cryptographic Accelerator supports four segments (0, 1, 2, and 3) within each data bus. Each segment contains 16 bytes. The end of packet (EOP) for a specific channel may occur in any of these segments (0, 1, 2, or 3). This feature is only available for the MACsec profile.

If EOP occurs in segments 1, 2, or 3, the subsequent segment can contain the start of packet (SOP) for another channel in supporting the MACsec profile for multi-packet mode.

The TID[31:0] signal specifies the stream and channel ID(s) for packet 0 and packet 1. Packet 0 supports both Single Packet Profile and Multi Packet Profile. Packet 1 supports Multi Packet Profile. Packet 0 is a starting packet in a MACsec profile or the only packet in the cycle. Packet 1 is an ending packet in the cycle in a MACsec profile.

  • TID[31:16]—Stream ID for packet 1
  • TID[25:16]—Channel ID for packet 1
  • TID[15:10]—Stream ID for packet 0
  • TID[9:0]—Channel ID for packet 0
The TID[31:0] signal is valid on the first clock cycle when tvalid signal is asserted.

The IP allows only a single SOP per any clock cycle. Sending multiple SOPs per the same cycle is not allowed. Similarly, only a single EOP per any clock cycle is allowed. If two packets are present within the same cycle, both packets must be the same stream.

The Symmetric Cryptographic IP core implements per stream register on AXI-ST RX data path MAC Security profile to store the channel ID of the first packet, packet 0. The IP core stares the channel ID at the start of the packet (SOP). When the IP core observes 2 packets within the same cycle, the previously stored channel ID belongs the packet 1 and the IP core stores the channel ID of the new packet 0 into the per stream register. When the AES/SM4 Inline Cryptographic Accelerator sends the EOP signal, the stored channel ID is assigned to the TID signal.

In the example below, the Symmetric Cryptographic IP core receives 4 requests from stream 0 and stream 1: during the cycle 0, the stream 0 EOP packet 1 accessing channel 1 and SOP packet 0 accesses channel 4. In cycle 1, the stream 1 EOP packet 1 is accessing channel 6 and SOP packet 0 accesses channel 7.
Table 28.  Example of Stream and Channel ID Buffering
Cycle 0 1 2 3
Profile MACsec MACsec MACsec MACsec
tvalid 1 1 1 1
tlast 1 1 0 0
tuser.TID[31:0]={Stream ID for Pkt 1, Channel ID for Pkt 1, Stream ID for Pkt 0, Channel ID for Pkt 0}
TID[31:26] 0 1 X X
TID[25:16] 1 6 X X
TID[15:10] 0 1 0 1
TID[9:0] 4 7 4 7
tkeep All 1s All 1s All 1s All 1s
DATA
tdata[127:0] EOP (Pkt 1) Data (Pkt 1) Data (Pkt 0) Data (Pkt 0)
tdata[255:128] SOP (Pkt 0) EOP (Pkt 1) Data (Pkt 0) Data (Pkt 0)
tdata[391:256] Data (Pkt 0) Idle Data (Pkt 0) Data (Pkt 0)
tdata[511:392] Data (Pkt 0) SOP (Pkt 0) Data (Pkt 0) Data (Pkt 0)

Internally, the Symmetric Cryptographic IP core stores the packet 1 channel 1 and 6 into stream 0 and 1 registers respectively during the SOP. When the AES/SM4 Inline Cryptographic Accelerator returns the EOP, the soft logic extracts the channel ID from the stream register and appends it to the TID[31:16] and sends it to the customer logic. The TID[15:0] is assigned with the stream and channel ID based on the packet with the SOP in the same cycle.

In Multi Packet Mode, 32 bits of TID are used to indicate the Stream and Channel ID for both packet within same cycle. In Single Packet Mode, only 16 bits of TID are used to indicate the Stream and Channel ID for the single packet. Upper 16 bits of TID (packet 1) are ignored.

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