Visible to Intel only — GUID: ccc1643655309832
Ixiasoft
Visible to Intel only — GUID: ccc1643655309832
Ixiasoft
7.1. Cryptographic Primary Control Register
Offset | 0x00 |
Addressing Mode | 32-bits |
Description | Cryptographic primary control register. |
Bit | Name | Type | Reset | Description |
---|---|---|---|---|
31 | cif_err_rd_ena | RW | 0x1 | Enables the status error register reading. The error status registers use the i_crypto_clk clock domain and the sector_reset domain. To access the error status registers when i_crypto_clk is not available or when the sector_reset is asserted, you unset the cif_err_rd_ena signal bit. |
30 | Reserved | |||
29 | clear_all_status_registers | RW | 0x1 | When set, clears all status registers. |
28 | clear_error_register | RW | 0x1 | When set, clears the error status register. |
27:24 | Reserved | |||
23:20 | axi_st0_latency | RW | 0x7 | AXI-ST Latency for the first 256-bits AXI-ST Interface Specifies the number of additional pipeline stage between the AXI-ST initiator and a target. |
19:16 | axi_lite_latency | RW | 0x7 | AXI Lite Latency Specifies the number of additional pipeline stage between the AXI Lite initiator and a target. |
15 | Reserved | |||
14 | wallcounter_reset | RW | 0x0 | Resets the wall clock counter. |
13 | ccf_clk_en | RW | 0x0 | CCL Clock gate enable When set, |
12 | cif_clk_en | RW | 0x0 | |
11 | clear_ipsec_bridge_states | RW | 0x0 | When set, clears the IP SEC bridge packetizer and depacketizer states. |
10 | clear_macsec_bridge_states | RW | 0x0 | When set, clears the IP MACSEC bridge packetizer and depacketizer states. |
9 | clear_xts_bridge_states | RW | 0x0 | When set, clears the GCM bridge packetizer and depacketizer states. |
8 | clear_gcm_bridge_states | RW | 0x0 | When set, clears the GCM bridge packetizer and depacketizer states. |
7 | xts_disable_type | RW | 0x0 | |
6 | cts_disable_type | RW | 0x0 | |
5:4 | Reserved | |||
3 | axi_data_width_type | RW | 0x0 | When set, the AXI interface width is 2x256. Otherwise, the AXI width is 1x512. |
2 | sm4_disable_type | RW | 0x0 | When set, disables the cryptographic engine for the SM4 algorithm and forces the cryptographic IP to only operate in the AES mode. If AXI-ST ingress packet includes the AES tuser bit, error detection asserts on egress port during the data cycle. The sm4_disable_type is forced on when fmica_fuse_disable_sm4 is set. |
1 | aes_disable_type | RW | 0x0 | When set, disables the cryptographic engine for the AES algorithm and forces the cryptographic IP to only operate in the SM4 mode. If AXI-ST ingress packet includes the AES tuser bit, error detection asserts on egress port during the data cycle. The sm4_disable_type is forced on when fmica_fuse_disable_aes is set. |
0 | crypto_disable_type | RW | 0 | When set, disables the cryptographic engine for the AES and SM4 algorithms by asserting ccl_reset signal and gating-off the i_crypto_clk clock. If fmica_fuse_disable_aes and fmica_fuse_disable_sm4 are set, it forces to set the crypto_disable_type signal. |