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Ixiasoft
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
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Ixiasoft
5.1. Reset Sequencer
The reset sequencer manages soft and hard IP resets within the Symmetric Cryptographic IP core through the reset and reset acknowledgment signals.
Figure 10. Reset Sequencer Block Connections
The following steps describe the reset assertion flow:
- The subsystem_cold_rst_n assertion resets the entire Symmetric Cryptographic IP core. Each of the soft and hard IP blocks observes the reset signal assertion.
- The synchronous reset acknowledgment signal (rst_ack) asserts when the reset assertion has propagated through all of the logic.
- Each of the soft and hard IP blocks assert a corresponding reset acknowledgement signal back to the Reset Sequencer.
- The Reset Sequencer asserts the subsystem_cold_rst_ack_n signal to logic once the block receives the soft and hard IP blocks reset acknowledgement signals.
The following steps describe the reset deassertion flow:
- The subsystem_cold_rst_n signal deassertion triggers the reset deassertion to the entire Symmetric Cryptographic IP core. Consequently, each of the soft and hard IP blocks observes the reset signal de-assertion.
- The synchronous reset acknowledgment signal (rst_ack) deasserts when the reset deassertion propagated through all of the logic.
- Each of the soft and hard IP blocks deassert a corresponding reset acknowledgement signal back to the Reset Sequencer.
- The Reset Sequencer deasserts the subsystem_cold_rst_ack_n signal to logic once the block receives the soft and hard IP blocks reset acknowledgement signals from the soft and hard IP blocks.
Note: The Symmetric Cryptographic IP core keeps deasserting the ready signals on the AXI-ST and AXI-Lite interfaces until the AES/SM4 Inline Cryptographic Accelerator is fully out of reset and ready to accept the incoming packets.