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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Cryptographic IP Data Profiles
7. Configuration Registers
8. Design Example
9. Symmetric Cryptographic Intel FPGA Hard IP User Guide Archives
10. Document Revision History for the Symmetric Cryptographic Intel FPGA Hard IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Specifying the IP Core Parameters and Options
4.3. Generated File Structure
4.4. Symmetric Cryptographic IP Core Flow
4.5. Dynamically Disabling SM4 Capability
4.6. Error Handling
4.7. Error Reporting
4.8. Resetting the IP Core
4.9. Channel Definition and Allocation
4.10. Byte Ordering
4.11. AXI-ST Single Packet Mode
4.12. AXI-ST Multiple Packet Mode
7.1. Cryptographic Primary Control Register
7.2. Cryptographic Secondary Control Register
7.3. Cryptographic Primary Status Register
7.4. Cryptographic Error Status Register
7.5. Cryptographic Error Control Register
7.6. Cryptographic Packet Error Control 1 Register
7.7. Cryptographic Packet Error Control 2 Register
7.8. Cryptographic Error Code Control 1 Register
7.9. Cryptographic Error Code Control 2 Register
7.10. Cryptographic Error Code Internal Control Register
7.11. Cryptographic Internal Error Control Register
7.12. Cryptographic First Error Log Register
7.13. Cryptographic Packet Error Log 1 Register
7.14. Cryptographic Packet Error Log 2 Register
7.15. Cryptographic Internal Error Log Register
7.16. Cryptographic Wall Clock LSB Register
7.17. Cryptographic Wall Clock MSB Register
7.18. Ternary Control Register
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4.8. Resetting the IP Core
Follow these steps to bring the Symmetric Cryptographic IP core from user mode to the streaming mode. The streaming mode enables you to stream in packets to the Symmetric Cryptographic IP core:
- Assert the subsystem_cold_reset_n signal to reset the Symmetric Cryptographic IP core and enter the user mode.
- Verify that you have a stable clock to the i_crypto_clk, app_ip_st_clk, and app_ip_lite_clk clock signals. Assert the pll_lock signal.
- Wait for the subsystem_cold_rst_ack_n acknowledgement signal to assert.
- Deassert the subsystem_cold_reset_n signal to release the reset on the AES/SM4 Inline Cryptographic Accelerator subsystem and begin streaming in data.