Symmetric Cryptographic Intel FPGA Hard IP User Guide

ID 714305
Date 10/31/2022
Public

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8.2.2. Host Interface

Figure 27. Host Interface

The host interface is used to provide software access to the VSIP CSRs and to the Symmetric Cryptographic Intel FPGA Hard IP AXI-Lite Interface. The host interface is clocked by the board clock and uses the board reset.

The host interface consists of an JTAG to AVMM converter which connects to a host machine via JTAG and to the VSIP via AVMM Interface. Avalon Memory Mapped bridges provide the AVMM interfaces, enabling the host to access Global, VSIP Tx, VSIP Rx, and IOPLL CSRs. An AVMM-AXI bridge helps to convert the AVMM interface to an AXI-Lite interface which can access the Symmetric Cryptographic Intel FPGA Hard IP Registers.