MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

A.1. User Guide Revision History

Table 29.  MAX 10 FPGA Development Kit User Guide Revision History
Date Version Changes
September 2017 2017.09.07 Updated I/O standard voltage values in the On-Board Oscillators table in On-Board Oscillators
January 2017 2017.01.04 Corrected the following pin assignments in "10/100/1000 Ethernet PHY":
  • ENETA_TX_D1 on pin P5
  • ENETA_RX_ER on pin U2
  • ENET_MDIO on pin Y5
  • ENETB_TX_D2 on pin U3
  • ENETB_RS_D3 on pin R7
November 2015 2015.11.06
  • Updated "USB to UART" section.
  • Added note to "General User Input/Output section".
June 2015 2015.06.26
  • Updated "DDR3 Rev. B Board" section.
May 2015 2015.05.21
  • Added quad SPI content for Rev. B & C boards.
  • Corrected two PMOD pin signal names for Rev. B & C boards.
  • Changed four MAX 10 pins for DDR3 for Rev. C board only.
  • Changed two switch/signal names for SW2 for Rev. C board only.
  • Updated Switch and Jumper Settings section with VTAP description.
March 2015 2015.03.31 Initial release.
Level Two Title