MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.8.4. HSMC

The high-speed mezzanine card (HSMC) interface is based on the Samtec 0.5 mm pitch, surface-mount QTH/QSH family of connectors. It is designed to support a full SPI-4.2 interface (17 LVDS channels) and 3 input and output clocks as well as SMBus and JTAG signals.

Since MAX 10 does not have transceiver channels, the HSMC clock-data-recovery channels are left unconnected.

The HSMC interface has programmable bi-directional I/O pins that can be used as 2.5 V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

For more information about the HSMC specification such as signaling standards, signal integrity, compatible connectors, and mechanical information, refer to the High Speed Mezzanine Card (HSMC) Specification manual.

Table 31.  HSMC Schematic Signals
Board Reference (J2) Schematic Signal Name I/O Standard MAX® 10/ MAX® II Pin Number Description
33 HSMC_SDA 2.5 V CMOS inout AA19 Management serial data line
34 HSMC_SCL 2.5 V CMOS out Y18 Management serial clock line
35 HSMC_JTAG_TCK Part of chain A9 ( MAX® II) JTAG clock
36 HSMC_JTAG_TMS Part of chain A8 ( MAX® II) JTAG mode select
37 HSMC_JTAG_TDO Part of chain A7 ( MAX® II) JTAG data out
38 HSMC_JTAG_TDI Part of chain A6 ( MAX® II) JTAG data in
39 HSMC_CLK_OUT0 2.5 V CMOS clock output AA13 clock output 0
40 HSMC_CLK_IN0 2.5 V CMOS clock in N4 Clock input 0
41 HSMC_D0 2.5 V CMOS inout Y7 Data bus
42 HSMC_D1 2.5 V CMOS inout Y8 Data bus
43 HSMC_D2 2.5 V CMOS inout AB2 Data bus
44 HSMC_D3 2.5 V CMOS inout AB3 Data bus
47 HSMC_TX_D_P0 2.5 V CMOS inout or LVDS TX channels-p W3 Data bus
48 HSMC_RX_D_P0 2.5 V CMOS inout or LVDS RX channels-p V5 Data bus
49 HSMC_TX_D_N0 2.5 V CMOS inout or LVDS TX channels-n W4 Data bus
50 HSMC_RX_D_N0 1 2.5 V CMOS inout or LVDS RX channels-n V4 Data bus
53 HSMC_TX_D_P1 2.5 V CMOS inout or LVDS TX channels-p U7 Data bus
54 HSMC_RX_D_P1 1 2.5 V CMOS inout or LVDS RX channels-p Y2 Data bus
55 HSMC_TX_D_N1 2.5 V CMOS inout or LVDS TX channels-n U6 Data bus
56 HSMC_RX_D_N1 1 2.5 V CMOS inout or LVDS RX channels-n Y1 Data bus
59 HSMC_TX_D_P2 2.5 V CMOS inout or LVDS TX channels-p W6 Data bus
60 HSMC_RX_D_P2 1 2.5 V CMOS inout or LVDS RX channels-p AA20 Data bus
61 HSMC_TX_D_N2 2.5 V CMOS inout or LVDS TX channels-n W5 Data bus
62 HSMC_RX_D_N2 1 2.5 V CMOS inout or LVDS RX channels-n AA1 Data bus
65 HSMC_TX_D_P3 2.5 V CMOS inout or LVDS TX channels-p W8 Data bus
66 HSMC_RX_D_P3 1 2.5 V CMOS inout or LVDS RX channels-p AB8 Data bus
67 HSMC_TX_D_N3 2.5 V CMOS inout or LVDS TX channels-n W7 Data bus
68 HSMC_RX_D_N3 1 2.5 V CMOS inout or LVDS RX channels-n AA8 Data bus
71 HSMC_TX_D_P4 2.5 V CMOS inout or LVDS TX channels-p AA10 Data bus
72 HSMC_RX_D_P4 1 2.5 V CMOS inout or LVDS RX channels-p AB9 Data bus
73 HSMC_TX_D_N4 2.5 V CMOS inout or LVDS TX channels-n Y10 Data bus
74 HSMC_RX_D_N4 1 2.5 V CMOS inout or LVDS RX channels-n AA9 Data bus
77 HSMC_TX_D_P5 2.5 V CMOS inout or LVDS TX channels-p AA7 Data bus
78 HSMC_RX_D_P5 1 2.5 V CMOS inout or LVDS RX channels-p AB7 Data bus
79 HSMC_TX_D_N5 2.5 V CMOS inout or LVDS TX channels-n AA6 Data bus
80 HSMC_RX_D_N5 1 2.5 V CMOS inout or LVDS RX channels-n AB6 Data bus
83 HSMC_TX_D_P6 2.5 V CMOS inout or LVDS TX channels-p P10 Data bus
84 HSMC_RX_D_P6 1 2.5 V CMOS inout or LVDS RX channels-p Y4 Data bus
85 HSMC_TX_D_N6 2.5 V CMOS inout or LVDS TX channels-n R10 Data bus
86 HSMC_RX_D_N6 1 2.5 V CMOS inout or LVDS RX channels-n Y3 Data bus
89 HSMC_TX_D_P7 2.5 V CMOS inout or LVDS TX channels-p W10 Data bus
90 HSMC_RX_D_P7 1 2.5 V CMOS inout or LVDS RX channels-p AB5 Data bus
91 HSMC_TX_D_N7 2.5 V CMOS inout or LVDS TX channels-n W9 Data bus
92 HSMC_RX_D_N7 1 2.5 V CMOS inout or LVDS RX channels-n AA5 Data bus
95 HSMC_CLK_OUT_P1 2.5 V CMOS inout or LVDS clock out P13 Clock output 1
96 HSMC_CLK_IN_P1 2.5 V CMOS inout or LVDS clock in AA20 Clock input 1
97 HSMC_CLK_OUT_N1 2.5 V CMOS inout or LVDS clock out R13 Clock output 1
98 HSMC_CLK_IN_N1 2.5 V CMOS inout or LVDS clock in AB21 Clock input 1
101 HSMC_TX_D_P8 2.5 V CMOS inout or LVDS TX channels-p W14 Data bus
102 HSMC_RX_D_P8 1 2.5 V CMOS inout or LVDS RX channels-p W13 Data bus
103 HSMC_TX_D_N8 2.5 V CMOS inout or LVDS TX channels-n V13 Data bus
104 HSMC_RX_D_N8 1 2.5 V CMOS inout or LVDS RX channels-n W12 Data bus
107 HSMC_TX_D_P9 2.5 V CMOS inout or LVDS TX channels-p Y14 Data bus
108 HSMC_RX_D_P9 1 2.5 V CMOS inout or LVDS RX channels-p AB15 Data bus
109 HSMC_TX_D_N9 2.5 V CMOS inout or LVDS TX channels-n Y13 Data bus
110 HSMC_RX_D_N9 1 2.5 V CMOS inout or LVDS RX channels-n AA14 Data bus
113 HSMC_TX_D_P10 2.5 V CMOS inout or LVDS TX channels-p V16 Data bus
114 HSMC_RX_D_P10 1 2.5 V CMOS inout or LVDS RX channels-p Y16 Data bus
115 HSMC_TX_D_N10 2.5 V CMOS inout or LVDS TX channels-n U15 Data bus
116 HSMC_RX_D_N10 1 2.5 V CMOS inout or LVDS RX channels-n AA15 Data bus
119 HSMC_TX_D_P11 2.5 V CMOS inout or LVDS TX channels-p W16 Data bus
120 HSMC_RX_D_P11 1 2.5 V CMOS inout or LVDS RX channels-p AA16 Data bus
121 HSMC_TX_D_N11 2.5 V CMOS inout or LVDS TX channels-n V15 Data bus
122 HSMC_RX_D_N11 1 2.5 V CMOS inout or LVDS RX channels-n AB16 Data bus
125 HSMC_TX_D_P12 2.5 V CMOS inout or LVDS TX channels-p V17 Data bus
126 HSMC_RX_D_P12 1 2.5 V CMOS inout or LVDS RX channels-p AB18 Data bus
127 HSMC_TX_D_N12 2.5 V CMOS inout or LVDS TX channels-n W17 Data bus
128 HSMC_RX_D_N12 1 2.5 V CMOS inout or LVDS RX channels-n AB17 Data bus
131 HSMC_TX_D_P13 2.5 V CMOS inout or LVDS TX channels-p V12 Data bus
132 HSMC_RX_D_P13 1 2.5 V CMOS inout or LVDS RX channels-p Y11 Data bus
133 HSMC_TX_D_N13 2.5 V CMOS inout or LVDS TX channels-n V11 Data bus
134 HSMC_RX_D_N13 1 2.5 V CMOS inout or LVDS RX channels-n W11 Data bus
137 HSMC_TX_D_P14 2.5 V CMOS inout or LVDS TX channels-p P12 Data bus
138 HSMC_RX_D_P14 1 2.5 V CMOS inout or LVDS RX channels-p AB11 Data bus
139 HSMC_TX_D_N14 2.5 V CMOS inout or LVDS TX channels-n R12 Data bus
140 HSMC_RX_D_N14 1 2.5 V CMOS inout or LVDS RX channels-n AB10 Data bus
143 HSMC_TX_D_P15 2.5 V CMOS inout or LVDS TX channels-p AA12 Data bus
144 HSMC_RX_D_P15 1 2.5 V CMOS inout or LVDS RX channels-p AB13 Data bus
145 HSMC_TX_D_N15 2.5 V CMOS inout or LVDS TX channels-n AA11 Data bus
146 HSMC_RX_D_N15 1 2.5 V CMOS inout or LVDS RX channels-n AB12 Data bus
149 HSMC_TX_D_P16 2.5 V CMOS inout or LVDS TX channels-p Y17 Data bus
150 HSMC_RX_D_P16 1 2.5 V CMOS inout or LVDS RX channels-p AB20 Data bus
151 HSMC_TX_D_N16 2.5 V CMOS inout or LVDS TX channels-n AA17 Data bus
152 HSMC_RX_D_N16 1 2.5 V CMOS inout or LVDS RX channels-n AB19 Data bus
155 HSMC_CLK_OUT_P2 2.5 V CMOS inout or LVDS clock out W15 Clock output 2
156 HSMC_CLK_IN_P2 2.5 V CMOS inout or LVDS clock in V10 Clock input 2
157 HSMC_CLK_OUT_N2 2.5 V CMOS inout or LVDS clock out V14 Clock output 2
158 HSMC_CLK_IN_N2 2.5 V CMOS inout or LVDS clock in V9 Clock input 2
160 HSMC_PRSNTn 2.5 V AB14 Present
Related Information
1 MAX® 10 does not have internal termination for LVDS RX. Install a 100 ohm resistor to support LVDS RX on HSMC.
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