MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.9.3. Flash

The MAX® 10 FPGA Development Kit provides a 512 Mb (megabit) quad SPI flash memory. The Generic Quad SPI controller core is used by default to erase, read, and write quad SPI flash in reference designs of the Board Test System (BTS) installer.

If you use the parallel flash loader (PFL) IP to program the quad SPI flash, you need to generate a .pof (Programmer Object file) to configure the device.

Perform the following steps to generate a .pof file:

  1. Create a byte-order Quartus.ini file with the setting:
    PGMIO_SWAP_HEX_BYTE_DATA=ON
  2. Copy the .ini file to the project root directory and open the project with the Quartus® Prime software.
  3. Open Convert Programming Files tool to generate the .pof file.
Table 37.  Default Memory Map of the 512 Mb QSPI Flash
Block Description Size (KB) Address Range
Board test system scratch 512 0x03F8.0000 – 0x03FF.FFFF
User software 56640 0x0083.0000 – 0x03F7.FFFF
Factory software 4096 0x0043.0000 – 0x0082.FFFF
Zips(html, web content) 4096 0x0003.0000 – 0x0042.FFFF
Board information 64 0x0002.0000 – 0x0002.FFFF
Ethernet option bits 64 0x0001.0000 – 0x0001.FFFF
User design reset vector 64 0x0000.0000 – 0x0000.FFFF
Table 38.  Flash Pin Assignments, Schematic Signal Names, and Functions
Board Reference (U7) Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
U7.7 QSPI_CSn 3.3 V C2 Chip select
U7.16 QSPI_CLK 3.3 V B2 Clock
U7.3 QSPI_RESETn 3.3 V

W12

( MAX® II)

Reset
U7.15 QSPI_IO0 3.3 V C6 Address bus
U7.8 QSPI_IO1 3.3 V C3 Address bus
U7.9 QSPI_IO2 3.3 V C5 Address bus
U7.1 QSPI_IO3 3.3 V B1 Address bus
Level Two Title