MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.4. The Flash Tab

The Flash tab allows you to read and write flash memory on your board.
Figure 9. The Flash Tab (Detail)
Table 5.  Controls on the Flash Tab
Control Description
Read Reads the flash memory on your board. To see the flash memory contents, type a starting address in the text box and click Read. Values starting at the specified address appear in the table.
Write Writes the flash memory on your board. To update the flash memory contents, change values in the table and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.
Erase Erases flash memory.
Increment Test Starts an incrementing data pattern test to flash memory, limited to the 512 K test system scratch page.
Random Test Starts a random data pattern test to flash memory, limited to the 512 K test system scratch page.
Flash Memory Map Displays the flash memory map for the development board.
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