4.1. Board Overview
This topic provides a high-level list of the major components of the MAX® 10 FPGA development board.
Board Reference | Type | Description |
---|---|---|
Featured Devices | ||
U1 | FPGA | MAX MAX® 10 FPGA 10M50DAF484C6GES, 50K LEs, F484 package. |
U13 | CPLD | MAX II EPM1270 256-MBGA, 2.5 V/3.3 V, VCCINT for On-Board USB- Blaster II. |
U17 | Power Regulator | Enpirion® EN2342QI, PowerSoC voltage-mode synchronous step-down converter with integrated inductor. |
U22, U23, U27 | Power Regulator | Enpirion EN6337QI, PowerSoC DC-DC step-down converters with integrated inductor. |
U26 | Power Regulator | Enpirion EP5358LUI, 600 mA PowerSoC DC-DC step-down converters with integrated inductor. |
U24, U25 | Power Regulator | Enpirion EP5358HUI, 600 mA PowerSoC DC-DC step-down converters with integrated inductor. |
Configuration and Setup Elements | ||
J12 | On-Board (Embedded) USB-Blaster Blaster™ II | Type-B USB connector for programming and debugging the FPGA. |
J14 | 10-pin header | Optional JTAG direct via 10-pin header for external download cables. |
J20 | 2x10-pin header | 16 dual-purpose ADC channels are connected to the 2x10 header. |
SW2 | DIP configuration and user switch | SW2 Includes switches to control boot images, JTAG bypass and HSMC bypass. |
J7 | Jumper for the MAX 10 ADC | Connects potentiometer for providing adjustable voltage to the ADC. |
S5 | Pulse_nconfig push button | Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. |
S6 | CPU reset push button | Default reset for the FPGA logic. |
Status Elements | ||
D1 | Blue power LED | Illuminates when 12-V power is present. |
D2 | Green high-speed mezzanine card (HSMC) LED | Illuminates when the HSMC is present. |
D13, D14 | Green USB-UART LEDs | Illuminates when the USB-UART transmitter and receiver are in use. |
D20 | Configuration done LED | Illuminates when the FPGA is configured. |
D21, D22, D23 | Power LEDs | Indicates that 3.3 V, 2.5 V, 1.2 V are powered up successfully. |
Clock Circuitry | ||
X1 | Programmable Clock for ADC | Programmable oscillator for ADC with default frequency of 10 MHz. |
U2 | Programmable Clock | Four channel programmable oscillator with default frequencies of 25, 50, 100, 125 MHz. |
General User Input/Output | ||
S1, S2, S3, S4 | General user push buttons | Four user push buttons. Driven low when pressed. |
D15, D16, D17, D18, D19 | User LEDs | Four user LEDs. Illuminates when driven low. |
SW1, SW2.1 | User DIP switches | Quad user DIP switches. |
Memory Devices | ||
U5 | DDR3 SDRAM A memory | 64 Mx16. |
U6 | DDR3 SDRAM B memory | 128 Mx8. |
U7 | Quad serial peripheral interface (quad SPI) flash | 512 Mb. |
Communication Ports | ||
J2 | HSMC port | Provides 84 CMOS or 17 LVDS channels per HSMC specification. |
U9, U10 | Two Gigabit Ethernet ports
|
RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Marvell 88E1111 x 2 PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode. |
J4, J5 | Two Diligent Pmod™ connectors | 12-pin interface with 8 I/O signal pins used to connect low frequency, low I/O peripheral modules. |
J11 | Mini-USB 2.0 UART port | USB connector with USB-to-UART bridge for serial UART interface |
J12 | Mini-USB port | Embedded USB- Blaster II. |
Analog | ||
J18, J19 | SMA inputs | Two FPGA analog-to-digital converter (ADC). |
J20 | Header | 2x10 ADC. |
POT1 | Potentiometer | Input to ADC. |
J1 | SMA output | External 16 bit digital-to-analog converter (DAC) device. |
Video and Display Ports | ||
U8 | HDMI video output | 19-pin HDMI connector which provides a HDMI v1.4 video output of up to 1080p through an ADI (Analog Devices, Inc) PHY. |
Power Supply | ||
J15 | DC input jack | Accepts 12 V DC power supply. |
SW3 | Power switch | Switch to power on or off the board when power is supplied from the DC input jack. |