MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.1. On-Board Oscillators

Figure 22.  MAX® 10 FPGA Development Board Clocks
Table 24.  On-Board Oscillators
Source Schematic Signal Name Frequency (MHz) I/O Standard MAX® 10 FPGA Pin Number Application
X1 CLK_10_ADC 10.000 2.5 V CMOS N5 Programmable default 10 MHz clock for ADC
U2 CLK_25_ENET 25.000 2.5 V CMOS — Ethernet clock
U2 CLK_25_MAX10 25.000 2.5 V CMOS M8 MAX® 10 clock
U2 CLK_50_MAXII 25.000 2.5 V/3.3V CMOS — Clock for On-Board Intel® FPGA Download Cable II
U2 CLK_50_MAX10 50.000 2.5 V CMOS M9 MAX® 10 clock
U2 CLK_DDR3_100_N 100.000 Differential SSTL-15 N15 DDR3 clocks
U2 CLK_DDR3_100_P 100.000 Differential SSTL-15 N14 DDR3 clocks
U2 CLK_LVDS_125_N 125.000 2.5 V LVDS R11 LVDS clocks
U2 CLK_LVDS_125_P 125.000 2.5 V LVDS P11 LVDS clocks
Note: For signal CLK_50_MAXII, the output side voltage is 2.5 V and the input side voltage is 3.3 V. However, they are compatible electrically.
Note: For signals CLK_DDR3_100_P and CLK_DDR3_100_N, at the MAX® 10 input side, Differential SSTL-15 is used as I/O standard because this bank's VCCIO is 1.5 V.
Level Two Title