MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.7.2. Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.
Table 25.  Off-Board Clock Inputs
Source Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
HSMC HSMC_CLK_IN_N1 2.5 V AB21 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_P1 2.5 V AA20 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_N2 2.5 V V9 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_P2 2.5 V V10 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN0 2.5 V N4 Single-ended input from the installed HSMC cable or board.
Table 26.  Off-Board Clock Outputs
Source Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
HSMC HSMC_CLK_OUT_N1 2.5 V R13 LVDS output
HSMC HSMC_CLK_OUT_P1 2.5 V P13 LVDS output
HSMC HSMC_CLK_OUT_N2 2.5 V V14 LVDS output
HSMC HSMC_CLK_OUT_P2 2.5 V W15 LVDS output
HSMC HSMC_CLK_OUT0 2.5 V AA13 FPGA CMOS output (or GPIO)
Level Two Title