4.9.2. DDR3 Rev. C Board
Note: For your board's revision, look for the board serial number on the back the board at the bottom.
The MAX 10 FPGA provides full-speed support to a x16 DDR3 300-MHz interface by using a 1 Gbit x16 memory. Additionally, the MAX 10 supports the error correction code (ECC) feature.
Board Reference (U5 & U6) | Schematic Signal Name | MAX 10 FPGA Pin Number | I/O Standard | Description |
---|---|---|---|---|
U5.N3 - U6.K3 | DDR3_A0 | V20 | 1.5V SSTL | Address bus |
U5.P7 - U6.L7 | DDR3_A1 | D19 | 1.5V SSTL | Address bus |
U5.P3 - U6.L3 | DDR3_A2 | A21 | 1.5V SSTL | Address bus |
U5.N2 - U6.K2 | DDR3_A3 | U20 | 1.5V SSTL | Address bus |
U5.P8 - U6.L8 | DDR3_A4 | C20 | 1.5V SSTL | Address bus |
U5.P2 - U6.L2 | DDR3_A5 | F19 | 1.5V SSTL | Address bus |
U5.R8 - U6.M8 | DDR3_A6 | E21 | 1.5V SSTL | Address bus |
U5.R2 - U6.M2 | DDR3_A7 | B20 | 1.5V SSTL | Address bus |
U5.T8 - U6.N8 | DDR3_A8 | D22 | 1.5V SSTL | Address bus |
U5.R3 - U6.M3 | DDR3_A9 | E22 | 1.5V SSTL | Address bus |
U5.L7 - U6.H7 | DDR3_A10 | Y20 | 1.5V SSTL | Address bus |
U5.R7 - U6.M7 | DDR3_A11 | E20 | 1.5V SSTL | Address bus |
U5.N7 - U6.K7 | DDR3_A12 | J14 | 1.5V SSTL | Address bus |
U5.T3 - U6.N3 | DDR3_A13 | C22 | 1.5V SSTL | Address bus |
U5.M2 - U6.J2 | DDR3_BA0 | V22 | 1.5V SSTL | Bank address bus |
U5.N8 - U6.K8 | DDR3_BA1 | N18 | 1.5V SSTL | Bank address bus |
U5.M3 - U6.J3 | DDR3_BA2 | W22 | 1.5V SSTL | Bank address bus |
U5.K3 - U6.G3 | DDR3_CASn | U19 | 1.5V SSTL | Row address bus |
U5.K9 - U6.G9 | DDR3_CKE | W20 | 1.5V SSTL | Clock enable |
U5.J7 - U6.F7 | DDR3_CLK_P | D18 | Differential 1.5V SSTL | Differential output clock |
U5.K7 - U6.G7 | DDR3_CLK_N | E18 | Differential 1.5V SSTL | Differential output clock |
U5.L2 - U6.H2 | DDR3_CSn | Y22 | 1.5V SSTL | Chip select |
U5.E7 | DDR3_DM0 | J15 | 1.5V SSTL | Write mask byte lane 0 |
U5.D3 | DDR3_DM1 | N19 | 1.5V SSTL | Write mask byte lane 1 |
U6.B7 | DDR3_DM2 | T18 | 1.5V SSTL | Write mask byte lane 2 |
U5.E3 | DDR3_DQ0 | J18 | 1.5V SSTL | Data bus byte lane 0 |
U5.F7 | DDR3_DQ1 | K20 | 1.5V SSTL | Data bus byte lane 0 |
U5.F2 | DDR3_DQ2 | H18 | 1.5V SSTL | Data bus byte lane 0 |
U5.F8 | DDR3_DQ3 | K18 | 1.5V SSTL | Data bus byte lane 0 |
U5.H3 | DDR3_DQ4 | H19 | 1.5V SSTL | Data bus byte lane 0 |
U5.H8 | DDR3_DQ5 | J20 | 1.5V SSTL | Data bus byte lane 0 |
U5.G2 | DDR3_DQ6 | H20 | 1.5V SSTL | Data bus byte lane 0 |
U5.H7 | DDR3_DQ7 | K19 | 1.5V SSTL | Data bus byte lane 0 |
U5.D7 | DDR3_DQ8 | L20 | 1.5V SSTL | Data bus byte lane 1 |
U5.C3 | DDR3_DQ9 | M18 | 1.5V SSTL | Data bus byte lane 1 |
U5.C8 | DDR3_DQ10 | M20 | 1.5V SSTL | Data bus byte lane 1 |
U5.C2 | DDR3_DQ11 | M14 | 1.5V SSTL | Data bus byte lane 1 |
U5.A7 | DDR3_DQ12 | L18 | 1.5V SSTL | Data bus byte lane 1 |
U5.A2 | DDR3_DQ13 | M15 | 1.5V SSTL | Data bus byte lane 1 |
U5.B8 | DDR3_DQ14 | L19 | 1.5V SSTL | Data bus byte lane 1 |
U5.A3 | DDR3_DQ15 | N20 | 1.5V SSTL | Data bus byte lane 1 |
U6.B3 | DDR3_DQ16 | R14 | 1.5V SSTL | Data bus byte lane 2 |
U6.C7 | DDR3_DQ17 | P19 | 1.5V SSTL | Data bus byte lane 2 |
U6.C2 | DDR3_DQ18 | P14 | 1.5V SSTL | Data bus byte lane 2 |
U6.C8 | DDR3_DQ19 | R20 | 1.5V SSTL | Data bus byte lane 2 |
U6.E3 | DDR3_DQ20 | R15 | 1.5V SSTL | Data bus byte lane 2 |
U6.E8 | DDR3_DQ21 | T19 | 1.5V SSTL | Data bus byte lane 2 |
U6.D2 | DDR3_DQ22 | P15 | 1.5V SSTL | Data bus byte lane 2 |
U6.E7 | DDR3_DQ23 | P20 | 1.5V SSTL | Data bus byte lane 2 |
U5.F3 | DDR3_DQS_P0 | K14 | Differential 1.5V SSTL | Data strobe P byte lane 0 |
U5.G3 | DDR3_DQS_N0 | K15 | Differential 1.5V SSTL | Data strobe N byte lane 0 |
U5.C7 | DDR3_DQS_P1 | L14 | Differential 1.5V SSTL | Data strobe P byte lane 1 |
U5.B7 | DDR3_DQS_N1 | L15 | Differential 1.5V SSTL | Data strobe N byte lane 1 |
U6.C3 | DDR3_DQS_P2 | R18 | Differential 1.5V SSTL | Data strobe P byte lane 2 |
U6.D3 | DDR3_DQS_N2 | P18 | Differential 1.5V SSTL | Data strobe N byte lane 2 |
U5.K1 - U6.G1 | DDR3_ODT | W19 | 1.5V SSTL | On-die termination enable |
U5.J3 - U6.F3 | DDR3_RASn | V18 | 1.5V SSTL | Row address select |
U5.T2 - U6.N2 | DDR3_RESETn | B22 | 1.5V SSTL | Reset |
U5.L3 - U6.H3 | DDR3_WEn | Y21 | 1.5V SSTL | Write enable |
U5.L8 | DDR3_ZQ1 | — | 1.5V SSTL | ZQ impedance calibration |
U6.H8 | DDR3_ZQ2 | — | 1.5V SSTL | ZQ impedance calibration |