MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

1. Overview

The MAX® 10 FPGA development board provides a hardware platform for evaluating the performance and features of the Intel® MAX 10 device.

The development kit includes a RoHS- and CE-compliant MAX 10 FPGA Development board with the following components:

  • Featured Devices:
    • MAX 10 FPGA (10M50D, dual supply, F484 package)
    • Enpirion® EN2342QI 4 A PowerSoC Voltage-Mode Synchronous Step-Down Converter with Integrated Inductor Enpirion
    • EN6337QI 3 A High-Efficiency PowerSoC DC-DC Step-Down Converters with Integrated Inductor
    • Enpirion EP5358xUI 600 mA PowerSoC DC-DC Step-Down Converters with Integrated Inductor
    • MAX II CPLD – EPM1270M256C4N (On-board USB-Blaster™ II)

  • Programming and Configuration:
    • Embedded USB-Blaster II (JTAG)
    • Optional JTAG direct via 10-pin header

  • Memory Devices:
    • 64-Mx16 1 Gb DDR3 SDRAM with soft memory controller
    • 128-Mx8 1 Gb DDR3 SDRAM with soft memory controller
    • 512-Mb Quad serial peripheral interface (quad SPI) flash

  • Communication Ports:
    • Two Gigabit Ethernet (GbE) RJ-45 ports
      • Ethernet Port A (Bottom)
      • Ethernet Port B (Top)
    • One mini-USB2.0 UART
    • One high-definition multimedia interface (HDMI) video output
    • One universal high-speed mezzanine card (HSMC) connector
    • Two 12-pin Digilent Pmod™ compatible connectors

  • Analog:
    • Two MAX 10 FPGA analog-to-digital converter (ADC) SMA inputs
    • 2x10 ADC header
    • Potentiometer input to ADC
    • One external 16 bit digital-to-analog converter (DAC) device with SMA output

  • Clocking
    • 25 MHz single-ended, external oscillator clock source
    • Silicon labs clock generator with programmable frequency GUI

  • Mini-USB cable for on-board USB-Blaster™ II

  • 2A Power Supply and cord

  • Free Quartus® II Web Edition design software (download software and license from website)

  • Complete documentation
    • User manual, bill of materials, schematic, and board files


Section Content
General Description
Handling the Board

Level Two Title