MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.8.1. 10/100/1000 Ethernet PHY

The MAX® 10 FPGA Development Kit supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Triple-Speed Ethernet Intel® FPGA IP MAC function.
Table 27.  Ethernet PHY A Pin Assignments, Signal Names, and Functions
Board Reference (U9) Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
U9.8 ENETA_GTX_CLK 2.5V CMOS T5 125 MHz RGMII TX clock
U9.4 ENETA_TX_CLK 3.3V LVCMOS E10 25/2.5 MHz MII TX clock
U9.11 ENETA_TX_D0 2.5V CMOS R5 RGMII TX data 0
U9.12 ENETA_TX_D1 2.5V CMOS P5 RGMII TX data 1
U9.14 ENETA_TX_D2 2.5V CMOS W1 RGMII TX data 2
U9.16 ENETA_TX_D3 2.5V CMOS W2 RGMII TX data 3
U9.9 ENETA_TX_EN 2.5V CMOS R4 RGMII TX enable
U9.7 ENETA_TX_ER 2.5V CMOS P4 MII TX error
U9.2 ENETA_RX_CLK 2.5V CMOS P3 RGMII RX clock
U9.95 ENETA_RX_D0 2.5V CMOS N9 RGMII RX data 0
U9.92 ENETA_RX_D1 2.5V CMOS T1 RGMII RX data 1
U9.93 ENETA_RX_D2 2.5V CMOS N1 RGMII RX data 2
U9.91 ENETA_RX_D3 2.5V CMOS T3 RGMII RX data 3
U9.94 ENETA_RX_DV 2.5V CMOS T2 RGMII RX valid
U9.3 ENETA_RX_ER 2.5V CMOS U2 MII RX error
U9.28 ENETA_RESETN 2.5V CMOS V8 Device reset
U9.23 ENETA_INTn 2.5V CMOS V7 Management bus interrupt
U9.25 ENET_MDC 2.5V CMOS Y6 MDI clock
U9.24 ENET_MDIO 2.5V CMOS Y5 MDI data
U9.84 ENETA_RX_CRS 2.5V CMOS N8 MII Carrier Sense
U9.83 ENETA_RX_COL 2.5V CMOS P1 MII Collision
U9.55 CLK_25_ENET 2.5V CMOS — 25 MHz Reference clock
U9.70 ENETA_LED_DUPLEX 2.5 V CMOS — Duplex or collision LED
U9.76 ENETA_LED_LINK10 2.5 V CMOS — 10 Mb link LED
U9.74 ENETA_LED_LINK100 2.5V CMOS R9 100 Mb link LED
U9.73 ENETA_LED_LINK1000 2.5V CMOS — 1000 Mb link LED
U9.58, 69 ENETA_LED_RX 2.5V CMOS — RX data active LED
U9.61, 68 ENETA_LED_TX 2.5V CMOS — TX data active LED
U9.29 ENETA_MDI_P0 2.5V CMOS — MDI
U9.31 ENETA_MDI_N0 2.5V CMOS — MDI
U9.33 ENETA_MDI_P1 2.5V CMOS — MDI
U9.34 ENETA_MDI_N1 2.5V CMOS — MDI
U9.39 ENETA_MDI_P2 2.5V CMOS — MDI
U9.41 ENETA_MDI_N2 2.5V CMOS — MDI
U9.42 ENETA_MDI_P3 2.5V CMOS — MDI
U9.43 ENETA_MDI_N3 2.5V CMOS — MDI
Table 28.  Ethernet PHY B Pin Assignments, Signal Names and Functions
Board Reference (U10) Schematic Signal Name I/O Standard Max 10 FPGA Pin Number Description
U10.8 ENETB_GTX_CLK 2.5V CMOS T6 125 MHz RGMII TX clock
U10.4 ENETB_TX_CLK 3.3V LVCMOS E11 25/2.5 MHz MII TX clock
U10.11 ENETB_TX_D0 2.5V CMOS U1 RGMII TX data 0
U10.12 ENETB_TX_D1 2.5V CMOS V1 RGMII TX data 1
U10.14 ENETB_TX_D2 2.5V CMOS U3 RGMII TX data 2
U10.16 ENETB_TX_D3 2.5V CMOS U4 RGMII TX data 3
U10.9 ENETB_TX_EN 2.5V CMOS V3 RGMII TX enable
U10.7 ENETB_TX_ER 2.5V CMOS U5 MII TX error
U10.2 ENETB_RX_CLK 2.5V CMOS R3 RGMII RX clock
U10.95 ENETB_RX_D0 2.5V CMOS P8 RGMII RX data 0
U10.92 ENETB_RX_D1 2.5V CMOS M1 RGMII RX data 1
U10.93 ENETB_RX_D2 2.5V CMOS M2 RGMII RX data 2
U10.91 ENETB_RX_D3 2.5V CMOS R7 RGMII RX data 3
U10.94 ENETB_RX_DV 2.5V CMOS R1 RGMII RX valid
U10.3 ENETB_RX_ER 2.5V CMOS R2 MII RX error
U10.28 ENETB_RESETn 2.5V CMOS AB4 Device reset
U10.23 ENETB_INTn 2.5V CMOS AA3 Management bus interrupt
U10.25 ENET_MDC 2.5V CMOS Y6 MDI clock
U10.24 ENET_MDIO 2.5V CMOS Y5 MDI data
U10.84 ENETB_RX_CRS 2.5V CMOS N3 MII Carrier Sense
U10.83 ENETB_RX_COL 2.5V CMOS N2 MII Collision
U10.55 CLK_25_ENET 2.5V CMOS — 25 MHz Reference clock
U10.70 ENETB_LED_DUPLEX 2.5V CMOS — Duplex or collision LED
U10.76 ENETB_LED_LINK10 2.5V CMOS — 10 Mb link LED
U10.74 ENETB_LED_LINK100 2.5V CMOS P9 100 Mb link LED
U10.73 ENETB_LED_LINK1000 2.5V CMOS — 1000 Mb link LED
U10.58, 69 ENETB_LED_RX 2.5V CMOS — RX data active LED
U10.61, 65, 68 ENETB_LED_TX 2.5V CMOS — TX data active LED
U10.29 ENETB_MDI_P0 2.5V CMOS — MDI
U10.31 ENETB_MDI_N0 2.5V CMOS — MDI
U10.33 ENETB_MDI_P1 2.5V CMOS — MDI
U10.34 ENETB_MDI_N1 2.5V CMOS — MDI
U10.39 ENETB_MDI_P2 2.5V CMOS — MDI
U10.41 ENETB_MDI_N2 2.5V CMOS — MDI
U10.42 ENETB_MDI_P3 2.5V CMOS — MDI
U10.43 ENETB_MDI_N3 2.5V CMOS — MDI
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