MAX® 10 FPGA Development Kit User Guide

ID 683460
Date 11/21/2024
Public
Document Table of Contents

A.3. Configuration

The MAX® 10 FPGA Development Kit supports two configuration methods:
  • Configuration by downloading a .sof file to the FPGA. Any power cycling of the FPGA or reconfiguration powers up the FPGA to a blank state.
  • Programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof file. Any power cycling of the FPGA or reconfiguration powers up the FPGA in self-configuration mode, using the files stored in the CFM.
You can use two different Intel® FPGA Download Cable hardware components to program the .sof or .pof files:
  • Embedded Intel® FPGA Download Cable II, type-B connector (J12).
  • JTAG header (J14). Use an external Intel® FPGA Download Cable, Intel® FPGA Download Cable II, or Intel® FPGA Ethernet Cable. The external download cable connects to the board through the JTAG header (J14).