MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.8.3. HDMI Video Output

The MAX® 10 FPGA Development Kit supports one HDMI transmitter and one HDMI receptacle.

The transmitter incorporates HDMI v1.4 features, and is capable of supporting an input data rate up to 165 MHz (1080p at 60 Hz, UXGA at 60 Hz). The connection between HDMI transmitter and MAX 10 is established in Bank 7, and the communication can be done via I2C interface.

Table 30.  HDMI Pin Assignments, Signal Names and Functions
Board Reference (U8) Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
U8.62 HDMI_TX_D0 3.3 V A17 HDMI digital video data bus
U8.61 HDMI_TX_D1 3.3 V A18 HDMI digital video data bus
U8.60 HDMI_TX_D2 3.3 V A12 HDMI digital video data bus
U8.59 HDMI_TX_D3 3.3 V F16 HDMI digital video data bus
U8.58 HDMI_TX_D4 3.3 V A16 HDMI digital video data bus
U8.57 HDMI_TX_D5 3.3 V B12 HDMI digital video data bus
U8.56 HDMI_TX_D6 3.3 V F15 HDMI digital video data bus
U8.55 HDMI_TX_D7 3.3 V B11 HDMI digital video data bus
U8.54 HDMI_TX_D8 3.3 V A13 HDMI digital video data bus
U8.52 HDMI_TX_D9 3.3 V C15 HDMI digital video data bus
U8.50 HDMI_TX_D10 3.3 V C11 HDMI digital video data bus
U8.49 HDMI_TX_D11 3.3 V A11 HDMI digital video data bus
U8.48 HDMI_TX_D12 3.3 V A20 HDMI digital video data bus
U8.47 HDMI_TX_D13 3.3 V H13 HDMI digital video data bus
U8.46 HDMI_TX_D14 3.3 V E14 HDMI digital video data bus
U8.45 HDMI_TX_D15 3.3 V D12 HDMI digital video data bus
U8.44 HDMI_TX_D16 3.3 V C12 HDMI digital video data bus
U8.43 HDMI_TX_D17 3.3 V C19 HDMI digital video data bus
U8.42 HDMI_TX_D18 3.3 V C18 HDMI digital video data bus
U8.41 HDMI_TX_D19 3.3 V B19 HDMI digital video data bus
U8.40 HDMI_TX_D20 3.3 V B17 HDMI digital video data bus
U8.39 HDMI_TX_D21 3.3 V B16 HDMI digital video data bus
U8.38 HDMI_TX_D22 3.3 V C16 HDMI digital video data bus
U8.37 HDMI_TX_D23 3.3 V A15 HDMI digital video data bus
U8.53 HDMI_TX_CLK 3.3 V D6 Video clock
U8.63 HDMI_TX_DE 3.3 V C10 Video data enable
U8.64 HDMI_TX_HS 3.3 V A19 Vertical Synchronization
U8.2 HDMI_TX_VS 3.3 V J12 Horizontal Synchronization
U8.28 HDMI_TX_INT 3.3 V D15 Interrupt Signal
U8.35 HDMI_SCL 3.3 V A10 HDMI I2C clock
U8.36 HDMI_SDAX 3.3 V B15 HDMI I2C data
Level Two Title