MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.9.1. DDR3 Rev. B Board

Note: For your board's revision, look for the board serial number on the back of the board at the bottom. Refer to the Components in MAX 10 FPGA Development Kit (Bottom View) figure for more information.
The MAX® 10 FPGA provides full-speed support to a x16 DDR3 300-MHz interface by using a 1 Gbit x16 memory. Additionally, the MAX® 10 supports the error correction code (ECC) feature.
CAUTION:
The DDR3 address signals at F18, E19, F20, and F21 on Rev. B boards violate MAX® 10 external memory guidelines when implementing DDR3 on the 10M50 F484 device. Altera recommends you follow the MAX® 10 guidelines for your own board designs and utilize Quartus® Prime software to verify pin location compliance. Contact Altera support if you received DDR3 pin location errors for your Rev. B kit designs.
Table 35.  DDR3 Pin Assignments, Signal Names, and Functions
Board Reference (U5 & U6) Schematic Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
U5.N3 - U6.K3 DDR3_A0 1.5 V SSTL V20 Address bus
U5.P7 - U6.L7 DDR3_A1 1.5 V SSTL F20

Address bus

Refer to Caution statement above.

U5.P3 - U6.L3 DDR3_A2 1.5 V SSTL F18

Address bus

Refer to Caution statement above.

U5.N2 - U6.K2 DDR3_A3 1.5 V SSTL U20 Address bus
U5.P8 - U6.L8 DDR3_A4 1.5 V SSTL F21

Address bus

Refer to Caution statement above.

U5.P2 - U6.L2 DDR3_A5 1.5 V SSTL F19 Address bus
U5.R8 - U6.M8 DDR3_A6 1.5 V SSTL E21 Address bus
U5.R2 -U6.M2 DDR3_A7 1.5 V SSTL E19

Address bus

Refer to Caution statement above.

U5.T8 - U6.N8 DDR3_A8 1.5 V SSTL D22 Address bus
U5.R3 - U6.M3 DDR3_A9 1.5 V SSTL E22 Address bus
U5.L7 - U6.H7 DDR3_A10 1.5 V SSTL Y20 Address bus
U5.R7 - U6.M7 DDR3_A11 1.5 V SSTL E20 Address bus
U5.N7 - U6.K7 DDR3_A12 1.5 V SSTL J14 Address bus
U5.T3 - U6.N3 DDR3_A13 1.5 V SSTL C22 Address bus
U5.M2 - U6.J2 DDR3_BA0 1.5 V SSTL V22 Bank address bus
U5.N8 - U6.K8 DDR3_BA1 1.5 V SSTL N18 Bank address bus
U5.M3 - U6.J3 DDR3_BA2 1.5 V SSTL W22 Bank address bus
U5.K3 - U6.G3 DDR3_CASn 1.5 V SSTL U19 Row address bus
U5.K9 - U6.G9 DDR3_CKE 1.5 V SSTL W20 Clock enable
U5.J7 - U6.F7 DDR3_CLK_P Differential 1.5 V SSTL D18 Differential output clock
U5.K7 - U6.G7 DDR3_CLK_N Differential 1.5 V SSTL E18 Differential output clock
U5.L2 - U6.H2 DDR3_CSn 1.5 V SSTL Y22 Chip select
U5.E7 DDR3_DM0 1.5 V SSTL J15 Write mask byte lane 0
U5.D3 DDR3_DM1 1.5 V SSTL N19 Write mask byte lane 1
U6.B7 DDR3_DM2 1.5 V SSTL T18 Write mask byte lane 2
U5.E3 DDR3_DQ0 1.5 V SSTL J18 Data bus byte lane 0
U5.F7 DDR3_DQ1 1.5 V SSTL K20 Data bus byte lane 0
U5.F2 DDR3_DQ2 1.5 V SSTL H18 Data bus byte lane 0
U5.F8 DDR3_DQ3 1.5 V SSTL K18 Data bus byte lane 0
U5.H3 DDR3_DQ4 1.5 V SSTL H19 Data bus byte lane 0
U5.H8 DDR3_DQ5 1.5 V SSTL J20 Data bus byte lane 0
U5.G2 DDR3_DQ6 1.5 V SSTL H20 Data bus byte lane 0
U5.H7 DDR3_DQ7 1.5 V SSTL K19 Data bus byte lane 0
U5.D7 DDR3_DQ8 1.5 V SSTL L20 Data bus byte lane 1
U5.C3 DDR3_DQ9 1.5 V SSTL M18 Data bus byte lane 1
U5.C8 DDR3_DQ10 1.5 V SSTL M20 Data bus byte lane 1
U5.C2 DDR3_DQ11 1.5 V SSTL M14 Data bus byte lane 1
U5.A7 DDR3_DQ12 1.5 V SSTL L18 Data bus byte lane 1
U5.A2 DDR3_DQ13 1.5 V SSTL M15 Data bus byte lane 1
U5.B8 DDR3_DQ14 1.5 V SSTL L19 Data bus byte lane 1
U5.A3 DDR3_DQ15 1.5 V SSTL N20 Data bus byte lane 1
U6.B3 DDR3_DQ16 1.5 V SSTL R14 Data bus byte lane 2
U6.C7 DDR3_DQ17 1.5 V SSTL P19 Data bus byte lane 2
U6.C2 DDR3_DQ18 1.5 V SSTL P14 Data bus byte lane 2
U6.C8 DDR3_DQ19 1.5 V SSTL R20 Data bus byte lane 2
U6.E3 DDR3_DQ20 1.5 V SSTL R15 Data bus byte lane 2
U6.E8 DDR3_DQ21 1.5 V SSTL T19 Data bus byte lane 2
U6.D2 DDR3_DQ22 1.5 V SSTL P15 Data bus byte lane 2
U6.E7 DDR3_DQ23 1.5 V SSTL P20 Data bus byte lane 2
U5.F3 DDR3_DQS_P0 Differential 1.5 V SSTL K14 Data strobe P byte lane 0
U5.G3 DDR3_DQS_N0 Differential 1.5 V SSTL K15 Data strobe N byte lane 0
U5.C7 DDR3_DQS_P1 Differential 1.5 V SSTL L14 Data strobe P byte lane 1
U5.B7 DDR3_DQS_N1 Differential 1.5 V SSTL L15 Data strobe N byte lane 1
U6.C3 DDR3_DQS_P2 Differential 1.5 V SSTL R18 Data strobe P byte lane 2
U6.D3 DDR3_DQS_N2 Differential 1.5 V SSTL P18 Data strobe N byte lane 2
U5.K1 - U6.G1 DDR3_ODT 1.5 V SSTL W19 On-die termination enable
U5.J3 - U6.F3 DDR3_RASn 1.5 V SSTL V18 Row address select
U5.T2 - U6.N2 DDR3_RESETn 1.5 V SSTL B22 Reset
U5.L3 - U6.H3 DDR3_WEn 1.5 V SSTL Y21 Write enable
U5.L8 DDR3_ZQ1 1.5 V SSTL — ZQ impedance calibration
U6.H8 DDR3_ZQ2 1.5 V SSTL — ZQ impedance calibration
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