MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

B. Developer Resources

Use the following links to check the Intel® website for other related information.
Table 39.   MAX® 10 FPGA Development Kit References
Reference Description
MAX® 10 FPGA Development Kit page Latest board design files, reference designs, and kit installation for Windows* and Linux*.
Rocketboard.org Open-source community website supporting SoC development including Altera and Partner SoC development kit targets and related designs and documentation.
Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide Installing the SoC EDS and Arm DS-5. Preloader user guide. Hard Processor System (HPS) Flash programmer. Bare Metal and Linux* Compilers. Debugging.
AN 958: Board Design Guidelines Board design-related resources for Altera®  devices. Its goal is to help you implement successful high-speed PCBs that integrate device(s) and other elements.
MAX® 10 Power Management User Guide Describes the MAX® 10 device family's power-optimization features, power-up and power-down sequences, power distribution network, and power optimization techniques.
MAX® 10 FPGA Configuration User Guide Describes the features and guidelines to configure the MAX® 10 configuration RAM. MAX® 10 devices support configuration using the following interfaces: JTAG and internal flash.
Documentation: MAX® 10 MAX® 10 device documentation.
Cadence* Capture CIS Schematic Symbols MAX® 10 OrCAD symbols.
Level Two Title