MAX® 10 FPGA Development Kit User Guide

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ID 683460
Date 11/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation 2.4. Board Update Portal
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
2.4. Board Update Portal x
2.4.1. Step 1: Connect to the Board Update Portal 2.4.2. Step 2: Update the User Software Portion
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Featured Device A.3. Configuration A.4. Status Elements A.5. Setup Elements A.6. General User Input/Output A.7. Clock Circuitry A.8. Components and Interfaces A.9. Memory A.10. Power Distribution System
A.3. Configuration x
A.3.1. Using the Quartus® Prime Programmer A.3.2. Selecting the Internal Configuration Scheme A.3.3. Switch and Jumper Settings
A.7. Clock Circuitry x
A.7.1. On-Board Oscillators A.7.2. Off-Board Clock Input/Output
A.8. Components and Interfaces x
A.8.1. 10/100/1000 Ethernet PHY A.8.2. Digital-to-Analog Converter A.8.3. HDMI Video Output A.8.4. HSMC A.8.5. Pmod Connectors A.8.6. USB to UART
A.9. Memory x
A.9.1. DDR3 Rev. B Board A.9.2. DDR3 Rev. C Board A.9.3. Flash
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Board Test System
4. Document Revision History for the MAX® 10 FPGA Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

A.8.5. Pmod Connectors

The MAX® 10 FPGA Development Kit features two Digilent Pmod* compatible headers, which are used to connect low frequency, low I/O pin count peripheral modules.

The 12-pin version Pmod connector used in this kit provides 8 I/O signal pins. The peripheral module interface also encompasses a variant using I2C interface, and two or four wire MTE cables. The Pmod signals are connected to Bank 8.

Table 32.  Pmod A Pin Assignments, Signal Names, and Functions
Schematic Signal Name Schematic Share Bus Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
PMODA_D0 PMODA_IO0 3.3 V C7 In/Out
PMODA_D1 PMODA_IO1 3.3 V C8 In/Out
PMODA_D2 PMODA_IO2 3.3 V A6 In/Out
PMODA_D3 PMODA_IO3 3.3 V B7 In/Out
PMODA_D4 PMODA_IO4 3.3 V D8 In/Out
PMODA_D5 PMODA_IO5 3.3 V A4 In/Out
PMODA_D6 PMODA_IO6 3.3 V A5 In/Out
PMODA_D7 PMODA_IO7 3.3 V E9 In/Out
— VCC 3.3 V — Power
— GND — — Ground
Table 33.  Pmod B Pin Assignments, Signal Names, and Functions
Schematic Signal Name Schematic Share Bus Signal Name I/O Standard MAX® 10 FPGA Pin Number Description
PMODB_D0 PMODB_IO0 3.3 V E8 In/Out
PMODB_D1 PMODB_IO1 3.3 V D5 In/Out
PMODB_D2 PMODB_IO2 3.3 V B5 In/Out
PMODB_D3 PMODB_IO3 3.3 V C4 In/Out
PMODB_D4 PMODB_IO4 3.3 V A2 In/Out
PMODB_D5 PMODB_IO5 3.3 V A3 In/Out
PMODB_D6 PMODB_IO6 3.3 V B4 In/Out
PMODB_D7 PMODB_IO7 3.3 V B3 In/Out
— VCC 3.3 V — Power
— GND — — Ground
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