Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1. Mailbox Client Intel FPGA IP User Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.3

The Mailbox Cliet Itel® FPGA IP 1 is a bidge betwee a host ad the secue device maage (SDM). You use the Mailbox Cliet Itel® FPGA IP to sed commads ad eceive status fom SDM peipheal cliets2.

The Mailbox Cliet defies fuctios that the SDM us. The followig pe-defied fuctios ae available:
  • Readig the Chip ID
  • Readig tempeatue sesos
  • Readig voltage sesos
  • Readig ad witig exteal quad seial peipheal iteface (SPI) flash memoy
  • Pefomig emote system updates (RSU)
  • Eablig cyptogaphic sevices 4 3

The followig block diagam shows how to use the Mailbox Cliet Itel® FPGA IP i a iteactive sessio. The diagam also emphasizes diffeet ways of commuicatig with IP though the Host Cotolle.

Figue 1.  Mailbox Cliet Itel® FPGA IP System Block Diagam
This block diagam icludes the followig compoets:
  • Host Cotolle: povides possible ways of accessig the Mailbox Cliet Itel® FPGA IP. Use ay of the specified ways to commuicate with the host cotolle:
    • System Cosole with the JTAG to Avalo® Maste Bidge Itel® FPGA IP. The System Cosole povides a Tcl Cosole pae that you ca use to u the IP fuctios. The JTAG to Avalo® Maste Bidge Itel® FPGA IP taslates the commads it eceives fom the System Cosole to Avalo® memoy-mapped iteface fomat that the Mailbox Cliet Itel® FPGA IP equies.
    • Nios® II pocesso: seds commads to the Mailbox Cliet Itel® FPGA IP.
    • Custom logic: It seds commads to the Mailbox Cliet Itel® FPGA IP.
    • PCIe* Had IP
    • Etheet IP

  • Mailbox Cliet Itel® FPGA IP: dives commads ad eceives esposes fom the SDM. This compoet icludes FIFOs with a maximum depth of 1024 eties to stoe commads ad esposes. The Mailbox Cliet Itel® FPGA IP iteupt idicates whe the iput FIFO is full ad whe the output FIFO cotais valid data. You ca size these FIFOs to accommodate the commads the you ited to sed.

Itel povides a efeece desig that uses the System Cosole ad the JTAG maste to dive the Mailbox Cliet Itel® FPGA IP. I the Itel Desig Stoe, seach fo Agilex™ 7 FPGA - Mailbox Cliet Desig Example with QSPI flash Access ad Remote System Update to view the desig.


Sectio Cotet
Release Ifomatio
Device Family Suppot
Paametes
Mailbox Cliet Itel FPGA IP Coe Iteface Sigals
Mailbox Cliet Itel FPGA IP Avalo Memoy-Mapped Iteface
Commads ad Resposes
Specifyig the Commad ad Respose FIFO Depths
Eablig Cyptogaphic Sevices
Usig the Mailbox Cliet Itel FPGA IP
Accessig Quad SPI Flash Mailbox Cliet Itel FPGA IP Coe Use Case Examples
Nios II ad Nios V Pocessos HAL Dive
Mailbox Cliet Itel FPGA IP Use Guide Achives
Documet Revisio Histoy fo the Mailbox Cliet Itel FPGA IP Use Guide

Related Ifomatio
1 To obtai specific IP ames coveed by this documet, efe to the Release Ifomatio sectio of this documet.
2 Fo the full list of suppoted SDM-based devices, efe to the Device Family Suppot sectio of this documet.
3 This featue is available fo Agilex™ 7 devices i Quatus® Pime softwae vesio 21.3 o late.
4 This featue is available fo Agilex™ 5 devices i Quatus® Pime softwae vesio 24.1 o late.
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