Mailbox Client Intel® FPGA IPs User Guide

Download PDF
ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.1. Clock and Reset Interfaces

Table 4.  Clock ad Reset Itefaces
Sigal Role Width Diectio Desciptio
clk 1 Iput Iput clock to clock the Mailbox Cliet Itel® FPGA IP. The maximum fequecy is 250 MHz.
eset 1 Iput Reset that esets the Mailbox Cliet Itel® FPGA IP.

To eset the IP, asset the eset sigal high fo at least 2 clk cycles.

To esue the Mailbox Cliet Itel® FPGA IP fuctios coectly whe the device etes use mode, you desig must iclude the Reset Release Itel® FPGA IP to hold the eset util the FPGA fabic eteed use mode. Itel ecommeds usig a eset sychoize whe coectig the use eset o output of the Reset Release Itel® FPGA IP to the eset pot of the Mailbox Cliet Itel® FPGA IP. To implemet the eset sychoize, use the Reset Bidge Itel® FPGA IP available i the Platfom Desige.
Note: Fo IP istatiatio ad coectio guidelies i the Platfom Desige, efe to the Requied Commuicatio ad Host Compoets fo the Remote System Update Desig Example figue i the Statix® 10 Cofiguatio Use Guide.
Note: Fo IP istatiatio guidelies, efe to the espective device's Cofiguatio Use Guide.
iq 1 Output Iteupt sigal. Dives the value of the AND of the iteupt status ad iteupt eable egistes.
Related Ifomatio
Level Two Title